Integrated circuit layout design method, device and equipment
The invention discloses an integrated circuit layout design method, device and equipment. The method comprises the following steps: acquiring a layout element set in original layout data of the integrated circuit; searching a target layout element set corresponding to the layout element set from a m...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Patent |
| Sprache: | chi ; eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | DING KE DING ZHONG ZHANG CHONGQIAN |
| description | The invention discloses an integrated circuit layout design method, device and equipment. The method comprises the following steps: acquiring a layout element set in original layout data of the integrated circuit; searching a target layout element set corresponding to the layout element set from a model database, wherein the target layout element set meets a DRC verification requirement; and replacing the layout element set in the original layout data with the target layout element set. According to the embodiment of the invention, the layout element set in the original layout data can be replaced and adjusted, and new DRC abnormity cannot be generated after replacement, so that the modification and adjustment efficiency in the DRC verification process is improved.
本申请公开了一种集成电路版图设计方法、装置及设备。该方法包括：获取集成电路的原始版图数据中的版图元素集合；从模型数据库中查找到与所述版图元素集合对应的目标版图元素集合；所述目标版图元素集合满足DRC校验要求；将所述原始版图数据中的所述版图元素集合替换为所述目标版图元素集合。根据本申请实施例，能够将原始版图数据中的版图元素集合进行替换调整，并且替换后不会产生新的DRC异常，从而提升DRC校验过程中修改调整的效率。 |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN113792525A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN113792525A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN113792525A3</originalsourceid><addsrcrecordid>eNrjZLD1zCtJTS9KLElNUUjOLEouzSxRyEmszC8tUUhJLc5Mz1PITS3JyE_RAXLLMpNTFRLzUhRSC0szC3JT80p4GFjTEnOKU3mhNDeDoptriLOHbmpBfnxqcUFicmpeakm8s5-hobG5pZGpkamjMTFqAC16MEQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Integrated circuit layout design method, device and equipment</title><source>esp@cenet</source><creator>DING KE ; DING ZHONG ; ZHANG CHONGQIAN</creator><creatorcontrib>DING KE ; DING ZHONG ; ZHANG CHONGQIAN</creatorcontrib><description>The invention discloses an integrated circuit layout design method, device and equipment. The method comprises the following steps: acquiring a layout element set in original layout data of the integrated circuit; searching a target layout element set corresponding to the layout element set from a model database, wherein the target layout element set meets a DRC verification requirement; and replacing the layout element set in the original layout data with the target layout element set. According to the embodiment of the invention, the layout element set in the original layout data can be replaced and adjusted, and new DRC abnormity cannot be generated after replacement, so that the modification and adjustment efficiency in the DRC verification process is improved.
本申请公开了一种集成电路版图设计方法、装置及设备。该方法包括：获取集成电路的原始版图数据中的版图元素集合；从模型数据库中查找到与所述版图元素集合对应的目标版图元素集合；所述目标版图元素集合满足DRC校验要求；将所述原始版图数据中的所述版图元素集合替换为所述目标版图元素集合。根据本申请实施例，能够将原始版图数据中的版图元素集合进行替换调整，并且替换后不会产生新的DRC异常，从而提升DRC校验过程中修改调整的效率。</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20211214&DB=EPODOC&CC=CN&NR=113792525A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20211214&DB=EPODOC&CC=CN&NR=113792525A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>DING KE</creatorcontrib><creatorcontrib>DING ZHONG</creatorcontrib><creatorcontrib>ZHANG CHONGQIAN</creatorcontrib><title>Integrated circuit layout design method, device and equipment</title><description>The invention discloses an integrated circuit layout design method, device and equipment. The method comprises the following steps: acquiring a layout element set in original layout data of the integrated circuit; searching a target layout element set corresponding to the layout element set from a model database, wherein the target layout element set meets a DRC verification requirement; and replacing the layout element set in the original layout data with the target layout element set. According to the embodiment of the invention, the layout element set in the original layout data can be replaced and adjusted, and new DRC abnormity cannot be generated after replacement, so that the modification and adjustment efficiency in the DRC verification process is improved.
本申请公开了一种集成电路版图设计方法、装置及设备。该方法包括：获取集成电路的原始版图数据中的版图元素集合；从模型数据库中查找到与所述版图元素集合对应的目标版图元素集合；所述目标版图元素集合满足DRC校验要求；将所述原始版图数据中的所述版图元素集合替换为所述目标版图元素集合。根据本申请实施例，能够将原始版图数据中的版图元素集合进行替换调整，并且替换后不会产生新的DRC异常，从而提升DRC校验过程中修改调整的效率。</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLD1zCtJTS9KLElNUUjOLEouzSxRyEmszC8tUUhJLc5Mz1PITS3JyE_RAXLLMpNTFRLzUhRSC0szC3JT80p4GFjTEnOKU3mhNDeDoptriLOHbmpBfnxqcUFicmpeakm8s5-hobG5pZGpkamjMTFqAC16MEQ</recordid><startdate>20211214</startdate><enddate>20211214</enddate><creator>DING KE</creator><creator>DING ZHONG</creator><creator>ZHANG CHONGQIAN</creator><scope>EVB</scope></search><sort><creationdate>20211214</creationdate><title>Integrated circuit layout design method, device and equipment</title><author>DING KE ; DING ZHONG ; ZHANG CHONGQIAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN113792525A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2021</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>DING KE</creatorcontrib><creatorcontrib>DING ZHONG</creatorcontrib><creatorcontrib>ZHANG CHONGQIAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>DING KE</au><au>DING ZHONG</au><au>ZHANG CHONGQIAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrated circuit layout design method, device and equipment</title><date>2021-12-14</date><risdate>2021</risdate><abstract>The invention discloses an integrated circuit layout design method, device and equipment. The method comprises the following steps: acquiring a layout element set in original layout data of the integrated circuit; searching a target layout element set corresponding to the layout element set from a model database, wherein the target layout element set meets a DRC verification requirement; and replacing the layout element set in the original layout data with the target layout element set. According to the embodiment of the invention, the layout element set in the original layout data can be replaced and adjusted, and new DRC abnormity cannot be generated after replacement, so that the modification and adjustment efficiency in the DRC verification process is improved.
本申请公开了一种集成电路版图设计方法、装置及设备。该方法包括：获取集成电路的原始版图数据中的版图元素集合；从模型数据库中查找到与所述版图元素集合对应的目标版图元素集合；所述目标版图元素集合满足DRC校验要求；将所述原始版图数据中的所述版图元素集合替换为所述目标版图元素集合。根据本申请实施例，能够将原始版图数据中的版图元素集合进行替换调整，并且替换后不会产生新的DRC异常，从而提升DRC校验过程中修改调整的效率。</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | chi ; eng |
| recordid | cdi_epo_espacenet_CN113792525A |
| source | esp@cenet |
| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Integrated circuit layout design method, device and equipment |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-10T06%3A14%3A47IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=DING%20KE&rft.date=2021-12-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN113792525A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |