Semiconductor package
A semiconductor package includes a first substrate, a first chip structure and a second chip structure spaced apart from each other on the first substrate, a gap region being defined between the first and second chip structures, and a heat dissipation member covering the first chip structure, the se...
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creator | LYU JU-HYUN CHOI YOON-SEOK LEE SANG-HYON RYU HYOANG KIM CHUL-WOO |
description | A semiconductor package includes a first substrate, a first chip structure and a second chip structure spaced apart from each other on the first substrate, a gap region being defined between the first and second chip structures, and a heat dissipation member covering the first chip structure, the second chip structure, and the first substrate, the heat dissipation member including a first trench in an inner top surface of the heat dissipation member, wherein the first trench vertically overlaps with the gap region and has a width greater than a width of the gap region, and wherein the first trench vertically overlaps with at least a portion of a top surface of the first chip structure or a portion of a top surface of the second chip structure.
一种半导体封装,包括:第一基板;在第一基板上彼此间隔开的第一芯片结构和第二芯片结构,在第一芯片结构和第二芯片结构之间限定有间隙区域;以及覆盖第一芯片结构、第二芯片结构和第一基板的散热构件,该散热构件在该散热构件的内顶表面中包括第一沟槽,其中,第一沟槽与间隙区域竖直地重叠并且宽度大于间隙区域的宽度,并且其中第一沟槽至少与第一芯片结构的顶表面的一部分或第二芯片结构的顶表面的一部分竖直地重叠。 |
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一种半导体封装,包括:第一基板;在第一基板上彼此间隔开的第一芯片结构和第二芯片结构,在第一芯片结构和第二芯片结构之间限定有间隙区域;以及覆盖第一芯片结构、第二芯片结构和第一基板的散热构件,该散热构件在该散热构件的内顶表面中包括第一沟槽,其中,第一沟槽与间隙区域竖直地重叠并且宽度大于间隙区域的宽度,并且其中第一沟槽至少与第一芯片结构的顶表面的一部分或第二芯片结构的顶表面的一部分竖直地重叠。</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20211207&DB=EPODOC&CC=CN&NR=113764363A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20211207&DB=EPODOC&CC=CN&NR=113764363A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LYU JU-HYUN</creatorcontrib><creatorcontrib>CHOI YOON-SEOK</creatorcontrib><creatorcontrib>LEE SANG-HYON</creatorcontrib><creatorcontrib>RYU HYOANG</creatorcontrib><creatorcontrib>KIM CHUL-WOO</creatorcontrib><title>Semiconductor package</title><description>A semiconductor package includes a first substrate, a first chip structure and a second chip structure spaced apart from each other on the first substrate, a gap region being defined between the first and second chip structures, and a heat dissipation member covering the first chip structure, the second chip structure, and the first substrate, the heat dissipation member including a first trench in an inner top surface of the heat dissipation member, wherein the first trench vertically overlaps with the gap region and has a width greater than a width of the gap region, and wherein the first trench vertically overlaps with at least a portion of a top surface of the first chip structure or a portion of a top surface of the second chip structure.
一种半导体封装,包括:第一基板;在第一基板上彼此间隔开的第一芯片结构和第二芯片结构,在第一芯片结构和第二芯片结构之间限定有间隙区域;以及覆盖第一芯片结构、第二芯片结构和第一基板的散热构件,该散热构件在该散热构件的内顶表面中包括第一沟槽,其中,第一沟槽与间隙区域竖直地重叠并且宽度大于间隙区域的宽度,并且其中第一沟槽至少与第一芯片结构的顶表面的一部分或第二芯片结构的顶表面的一部分竖直地重叠。</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBANTs3NTM7PSylNLskvUihITM5OTE_lYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxUBVqXmpJfHOfoaGxuZmJsZmxo7GxKgBAIaSIUs</recordid><startdate>20211207</startdate><enddate>20211207</enddate><creator>LYU JU-HYUN</creator><creator>CHOI YOON-SEOK</creator><creator>LEE SANG-HYON</creator><creator>RYU HYOANG</creator><creator>KIM CHUL-WOO</creator><scope>EVB</scope></search><sort><creationdate>20211207</creationdate><title>Semiconductor package</title><author>LYU JU-HYUN ; CHOI YOON-SEOK ; LEE SANG-HYON ; RYU HYOANG ; KIM CHUL-WOO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN113764363A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LYU JU-HYUN</creatorcontrib><creatorcontrib>CHOI YOON-SEOK</creatorcontrib><creatorcontrib>LEE SANG-HYON</creatorcontrib><creatorcontrib>RYU HYOANG</creatorcontrib><creatorcontrib>KIM CHUL-WOO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LYU JU-HYUN</au><au>CHOI YOON-SEOK</au><au>LEE SANG-HYON</au><au>RYU HYOANG</au><au>KIM CHUL-WOO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor package</title><date>2021-12-07</date><risdate>2021</risdate><abstract>A semiconductor package includes a first substrate, a first chip structure and a second chip structure spaced apart from each other on the first substrate, a gap region being defined between the first and second chip structures, and a heat dissipation member covering the first chip structure, the second chip structure, and the first substrate, the heat dissipation member including a first trench in an inner top surface of the heat dissipation member, wherein the first trench vertically overlaps with the gap region and has a width greater than a width of the gap region, and wherein the first trench vertically overlaps with at least a portion of a top surface of the first chip structure or a portion of a top surface of the second chip structure.
一种半导体封装,包括:第一基板;在第一基板上彼此间隔开的第一芯片结构和第二芯片结构,在第一芯片结构和第二芯片结构之间限定有间隙区域;以及覆盖第一芯片结构、第二芯片结构和第一基板的散热构件,该散热构件在该散热构件的内顶表面中包括第一沟槽,其中,第一沟槽与间隙区域竖直地重叠并且宽度大于间隙区域的宽度,并且其中第一沟槽至少与第一芯片结构的顶表面的一部分或第二芯片结构的顶表面的一部分竖直地重叠。</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Semiconductor package |
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