Semiconductor structure and forming method thereof
A method includes forming a first dielectric layer, forming a first redistribution line including a first via extending into the first dielectric layer and a first trace over the first dielectric layer, forming a second dielectric layer overlying the first redistribution line, and patterning the sec...
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creator | LIN BAIYAO YANG ZHEJIA YE SHUSHEN LIN JIAXIANG XU JIAGUI ZHENG XINPU |
description | A method includes forming a first dielectric layer, forming a first redistribution line including a first via extending into the first dielectric layer and a first trace over the first dielectric layer, forming a second dielectric layer overlying the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is exposed through the via opening. The method further includes depositing a conductive material into the via opening to form a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, and the second via is offset from a centerline of the conductive bump. The embodiment of the invention also relates to a semiconductor structure and a forming method thereof.
方法包括形成第一介电层,形成第一再分布线,第一再分布线包括延伸至第一介电层中的第一通孔和位于第一介电层上方的第一迹线,形成覆盖第一再分布线的第二介电层,以及图案化第二介电层以形成通孔开口。第一再分布线通过通孔开口露出。方法还包括将导电材料沉积至通孔开口中以在第二介电层中形成 |
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方法包括形成第一介电层,形成第一再分布线,第一再分布线包括延伸至第一介电层中的第一通孔和位于第一介电层上方的第一迹线,形成覆盖第一再分布线的第二介电层,以及图案化第二介电层以形成通孔开口。第一再分布线通过通孔开口露出。方法还包括将导电材料沉积至通孔开口中以在第二介电层中形成</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20211102&DB=EPODOC&CC=CN&NR=113594045A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20211102&DB=EPODOC&CC=CN&NR=113594045A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LIN BAIYAO</creatorcontrib><creatorcontrib>YANG ZHEJIA</creatorcontrib><creatorcontrib>YE SHUSHEN</creatorcontrib><creatorcontrib>LIN JIAXIANG</creatorcontrib><creatorcontrib>XU JIAGUI</creatorcontrib><creatorcontrib>ZHENG XINPU</creatorcontrib><title>Semiconductor structure and forming method thereof</title><description>A method includes forming a first dielectric layer, forming a first redistribution line including a first via extending into the first dielectric layer and a first trace over the first dielectric layer, forming a second dielectric layer overlying the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is exposed through the via opening. The method further includes depositing a conductive material into the via opening to form a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, and the second via is offset from a centerline of the conductive bump. The embodiment of the invention also relates to a semiconductor structure and a forming method thereof.
方法包括形成第一介电层,形成第一再分布线,第一再分布线包括延伸至第一介电层中的第一通孔和位于第一介电层上方的第一迹线,形成覆盖第一再分布线的第二介电层,以及图案化第二介电层以形成通孔开口。第一再分布线通过通孔开口露出。方法还包括将导电材料沉积至通孔开口中以在第二介电层中形成</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAKTs3NTM7PSylNLskvUiguKQIySotSFRLzUhTS8otyM_PSFXJTSzLyUxRKMlKLUvPTeBhY0xJzilN5oTQ3g6Kba4izh25qQX58anFBYnJqXmpJvLOfoaGxqaWJgYmpozExagAPQiyc</recordid><startdate>20211102</startdate><enddate>20211102</enddate><creator>LIN BAIYAO</creator><creator>YANG ZHEJIA</creator><creator>YE SHUSHEN</creator><creator>LIN JIAXIANG</creator><creator>XU JIAGUI</creator><creator>ZHENG XINPU</creator><scope>EVB</scope></search><sort><creationdate>20211102</creationdate><title>Semiconductor structure and forming method thereof</title><author>LIN BAIYAO ; YANG ZHEJIA ; YE SHUSHEN ; LIN JIAXIANG ; XU JIAGUI ; ZHENG XINPU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN113594045A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LIN BAIYAO</creatorcontrib><creatorcontrib>YANG ZHEJIA</creatorcontrib><creatorcontrib>YE SHUSHEN</creatorcontrib><creatorcontrib>LIN JIAXIANG</creatorcontrib><creatorcontrib>XU JIAGUI</creatorcontrib><creatorcontrib>ZHENG XINPU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LIN BAIYAO</au><au>YANG ZHEJIA</au><au>YE SHUSHEN</au><au>LIN JIAXIANG</au><au>XU JIAGUI</au><au>ZHENG XINPU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor structure and forming method thereof</title><date>2021-11-02</date><risdate>2021</risdate><abstract>A method includes forming a first dielectric layer, forming a first redistribution line including a first via extending into the first dielectric layer and a first trace over the first dielectric layer, forming a second dielectric layer overlying the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is exposed through the via opening. The method further includes depositing a conductive material into the via opening to form a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, and the second via is offset from a centerline of the conductive bump. The embodiment of the invention also relates to a semiconductor structure and a forming method thereof.
方法包括形成第一介电层,形成第一再分布线,第一再分布线包括延伸至第一介电层中的第一通孔和位于第一介电层上方的第一迹线,形成覆盖第一再分布线的第二介电层,以及图案化第二介电层以形成通孔开口。第一再分布线通过通孔开口露出。方法还包括将导电材料沉积至通孔开口中以在第二介电层中形成</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Semiconductor structure and forming method thereof |
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