Isolated interface integrated circuit and packaging method thereof
The invention provides an isolated interface integrated circuit and method, and belongs to the technical field of integrated circuits. The isolated interface integrated circuit comprises a digital channel primary end chip DIE1 and a power channel primary end chip DIE5 which are arranged on a first b...
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| creator | LUO HEPING GAO YUZHU YUAN SITONG WANG ZUO WEN SHOUFU |
| description | The invention provides an isolated interface integrated circuit and method, and belongs to the technical field of integrated circuits. The isolated interface integrated circuit comprises a digital channel primary end chip DIE1 and a power channel primary end chip DIE5 which are arranged on a first base island, a digital channel isolation device chip DIE2, a digital channel secondary end chip DIE3 and a bus interface chip DIE4 which are arranged on a second base island, and a power channel isolation device chip DIE6 and a power channel secondary end chip DIE7 which are arranged on a third base island, and the first base island, the second base island and the third base island are mutually isolated. According to the present invention, a packaging method for a multi-DIE integrated isolated interface is simple in process and low in cost, and an isolated DC-DC power source and an isolated interface chip are integrated together, so that the chip only needs to supply power at the original end, no extra power source |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN113506793A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN113506793A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN113506793A3</originalsourceid><addsrcrecordid>eNrjZHDyLM7PSSxJTVHIzCtJLUpLTE4Fs9KLwILJmUXJpZklCol5KQoFicnZiemZeekKuaklGfkpCiUZqUWp-Wk8DKxpiTnFqbxQmptB0c01xNlDN7UgPz61GKgtNS-1JN7Zz9DQ2NTAzNzS2NGYGDUAYq0yVQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Isolated interface integrated circuit and packaging method thereof</title><source>esp@cenet</source><creator>LUO HEPING ; GAO YUZHU ; YUAN SITONG ; WANG ZUO ; WEN SHOUFU</creator><creatorcontrib>LUO HEPING ; GAO YUZHU ; YUAN SITONG ; WANG ZUO ; WEN SHOUFU</creatorcontrib><description>The invention provides an isolated interface integrated circuit and method, and belongs to the technical field of integrated circuits. The isolated interface integrated circuit comprises a digital channel primary end chip DIE1 and a power channel primary end chip DIE5 which are arranged on a first base island, a digital channel isolation device chip DIE2, a digital channel secondary end chip DIE3 and a bus interface chip DIE4 which are arranged on a second base island, and a power channel isolation device chip DIE6 and a power channel secondary end chip DIE7 which are arranged on a third base island, and the first base island, the second base island and the third base island are mutually isolated. According to the present invention, a packaging method for a multi-DIE integrated isolated interface is simple in process and low in cost, and an isolated DC-DC power source and an isolated interface chip are integrated together, so that the chip only needs to supply power at the original end, no extra power source</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20211015&DB=EPODOC&CC=CN&NR=113506793A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20211015&DB=EPODOC&CC=CN&NR=113506793A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LUO HEPING</creatorcontrib><creatorcontrib>GAO YUZHU</creatorcontrib><creatorcontrib>YUAN SITONG</creatorcontrib><creatorcontrib>WANG ZUO</creatorcontrib><creatorcontrib>WEN SHOUFU</creatorcontrib><title>Isolated interface integrated circuit and packaging method thereof</title><description>The invention provides an isolated interface integrated circuit and method, and belongs to the technical field of integrated circuits. The isolated interface integrated circuit comprises a digital channel primary end chip DIE1 and a power channel primary end chip DIE5 which are arranged on a first base island, a digital channel isolation device chip DIE2, a digital channel secondary end chip DIE3 and a bus interface chip DIE4 which are arranged on a second base island, and a power channel isolation device chip DIE6 and a power channel secondary end chip DIE7 which are arranged on a third base island, and the first base island, the second base island and the third base island are mutually isolated. According to the present invention, a packaging method for a multi-DIE integrated isolated interface is simple in process and low in cost, and an isolated DC-DC power source and an isolated interface chip are integrated together, so that the chip only needs to supply power at the original end, no extra power source</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHDyLM7PSSxJTVHIzCtJLUpLTE4Fs9KLwILJmUXJpZklCol5KQoFicnZiemZeekKuaklGfkpCiUZqUWp-Wk8DKxpiTnFqbxQmptB0c01xNlDN7UgPz61GKgtNS-1JN7Zz9DQ2NTAzNzS2NGYGDUAYq0yVQ</recordid><startdate>20211015</startdate><enddate>20211015</enddate><creator>LUO HEPING</creator><creator>GAO YUZHU</creator><creator>YUAN SITONG</creator><creator>WANG ZUO</creator><creator>WEN SHOUFU</creator><scope>EVB</scope></search><sort><creationdate>20211015</creationdate><title>Isolated interface integrated circuit and packaging method thereof</title><author>LUO HEPING ; GAO YUZHU ; YUAN SITONG ; WANG ZUO ; WEN SHOUFU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN113506793A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LUO HEPING</creatorcontrib><creatorcontrib>GAO YUZHU</creatorcontrib><creatorcontrib>YUAN SITONG</creatorcontrib><creatorcontrib>WANG ZUO</creatorcontrib><creatorcontrib>WEN SHOUFU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LUO HEPING</au><au>GAO YUZHU</au><au>YUAN SITONG</au><au>WANG ZUO</au><au>WEN SHOUFU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Isolated interface integrated circuit and packaging method thereof</title><date>2021-10-15</date><risdate>2021</risdate><abstract>The invention provides an isolated interface integrated circuit and method, and belongs to the technical field of integrated circuits. The isolated interface integrated circuit comprises a digital channel primary end chip DIE1 and a power channel primary end chip DIE5 which are arranged on a first base island, a digital channel isolation device chip DIE2, a digital channel secondary end chip DIE3 and a bus interface chip DIE4 which are arranged on a second base island, and a power channel isolation device chip DIE6 and a power channel secondary end chip DIE7 which are arranged on a third base island, and the first base island, the second base island and the third base island are mutually isolated. According to the present invention, a packaging method for a multi-DIE integrated isolated interface is simple in process and low in cost, and an isolated DC-DC power source and an isolated interface chip are integrated together, so that the chip only needs to supply power at the original end, no extra power source</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Isolated interface integrated circuit and packaging method thereof |
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