Preparation process of silicon substrate on power insulator
The invention relates to a preparation process of a silicon substrate on a power insulator. The preparation process comprises the following steps: preparing a silicon epitaxial wafer as a device layer silicon substrate and an oxidized silicon wafer as a supporting silicon substrate, performing plasm...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | chi ; eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | SUN CHENGUANG MA QIANZHI WANG YANJUN |
description | The invention relates to a preparation process of a silicon substrate on a power insulator. The preparation process comprises the following steps: preparing a silicon epitaxial wafer as a device layer silicon substrate and an oxidized silicon wafer as a supporting silicon substrate, performing plasma surface activation treatment, performing low-temperature annealing after normal-temperature bonding, and performing low-temperature annealing after adopting a mechanical grinding thinning mode, removing a silicon single crystal of the substrate by using two-step selective acid corrosion of fast corrosion and slow corrosion, carrying out CMP polishing treatment, then carrying out high-temperature oxidation thinning treatment, and finally removing silicon oxide grown by high-temperature oxidation through diluted hydrofluoric acid corrosion; enabling the low-temperature annealing temperature after bonding to not exceed 400 DEG C; and enabling the polishing removal amount of the bonding wafer to not exceed 1 micron a |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN113421848A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN113421848A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN113421848A3</originalsourceid><addsrcrecordid>eNrjZLAOKEotSCxKLMnMz1MoKMpPTi0uVshPUyjOzMlMBgoVlyYVlwClUxVA8vnlqUUKmXnFpTmJJflFPAysaYk5xam8UJqbQdHNNcTZQze1ID8-tbggMTk1L7Uk3tnP0NDYxMjQwsTC0ZgYNQD7ljAU</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Preparation process of silicon substrate on power insulator</title><source>esp@cenet</source><creator>SUN CHENGUANG ; MA QIANZHI ; WANG YANJUN</creator><creatorcontrib>SUN CHENGUANG ; MA QIANZHI ; WANG YANJUN</creatorcontrib><description>The invention relates to a preparation process of a silicon substrate on a power insulator. The preparation process comprises the following steps: preparing a silicon epitaxial wafer as a device layer silicon substrate and an oxidized silicon wafer as a supporting silicon substrate, performing plasma surface activation treatment, performing low-temperature annealing after normal-temperature bonding, and performing low-temperature annealing after adopting a mechanical grinding thinning mode, removing a silicon single crystal of the substrate by using two-step selective acid corrosion of fast corrosion and slow corrosion, carrying out CMP polishing treatment, then carrying out high-temperature oxidation thinning treatment, and finally removing silicon oxide grown by high-temperature oxidation through diluted hydrofluoric acid corrosion; enabling the low-temperature annealing temperature after bonding to not exceed 400 DEG C; and enabling the polishing removal amount of the bonding wafer to not exceed 1 micron a</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210921&DB=EPODOC&CC=CN&NR=113421848A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210921&DB=EPODOC&CC=CN&NR=113421848A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SUN CHENGUANG</creatorcontrib><creatorcontrib>MA QIANZHI</creatorcontrib><creatorcontrib>WANG YANJUN</creatorcontrib><title>Preparation process of silicon substrate on power insulator</title><description>The invention relates to a preparation process of a silicon substrate on a power insulator. The preparation process comprises the following steps: preparing a silicon epitaxial wafer as a device layer silicon substrate and an oxidized silicon wafer as a supporting silicon substrate, performing plasma surface activation treatment, performing low-temperature annealing after normal-temperature bonding, and performing low-temperature annealing after adopting a mechanical grinding thinning mode, removing a silicon single crystal of the substrate by using two-step selective acid corrosion of fast corrosion and slow corrosion, carrying out CMP polishing treatment, then carrying out high-temperature oxidation thinning treatment, and finally removing silicon oxide grown by high-temperature oxidation through diluted hydrofluoric acid corrosion; enabling the low-temperature annealing temperature after bonding to not exceed 400 DEG C; and enabling the polishing removal amount of the bonding wafer to not exceed 1 micron a</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAOKEotSCxKLMnMz1MoKMpPTi0uVshPUyjOzMlMBgoVlyYVlwClUxVA8vnlqUUKmXnFpTmJJflFPAysaYk5xam8UJqbQdHNNcTZQze1ID8-tbggMTk1L7Uk3tnP0NDYxMjQwsTC0ZgYNQD7ljAU</recordid><startdate>20210921</startdate><enddate>20210921</enddate><creator>SUN CHENGUANG</creator><creator>MA QIANZHI</creator><creator>WANG YANJUN</creator><scope>EVB</scope></search><sort><creationdate>20210921</creationdate><title>Preparation process of silicon substrate on power insulator</title><author>SUN CHENGUANG ; MA QIANZHI ; WANG YANJUN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN113421848A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>SUN CHENGUANG</creatorcontrib><creatorcontrib>MA QIANZHI</creatorcontrib><creatorcontrib>WANG YANJUN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SUN CHENGUANG</au><au>MA QIANZHI</au><au>WANG YANJUN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Preparation process of silicon substrate on power insulator</title><date>2021-09-21</date><risdate>2021</risdate><abstract>The invention relates to a preparation process of a silicon substrate on a power insulator. The preparation process comprises the following steps: preparing a silicon epitaxial wafer as a device layer silicon substrate and an oxidized silicon wafer as a supporting silicon substrate, performing plasma surface activation treatment, performing low-temperature annealing after normal-temperature bonding, and performing low-temperature annealing after adopting a mechanical grinding thinning mode, removing a silicon single crystal of the substrate by using two-step selective acid corrosion of fast corrosion and slow corrosion, carrying out CMP polishing treatment, then carrying out high-temperature oxidation thinning treatment, and finally removing silicon oxide grown by high-temperature oxidation through diluted hydrofluoric acid corrosion; enabling the low-temperature annealing temperature after bonding to not exceed 400 DEG C; and enabling the polishing removal amount of the bonding wafer to not exceed 1 micron a</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | chi ; eng |
recordid | cdi_epo_espacenet_CN113421848A |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Preparation process of silicon substrate on power insulator |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-22T12%3A03%3A04IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SUN%20CHENGUANG&rft.date=2021-09-21&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN113421848A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |