Semiconductor device and method of making the same
An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surfa...
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creator | LIN JIANLONG LIN SHIHAO LIN JIANZHI YANG ZHIQUAN SU XINWEN |
description | An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.
N型金属氧化物半导体(NMOS)晶体管包括第一栅极和沿第一方向设置在第一栅极的第一侧壁上的第一间隔件结构。第一间隔件结构在第一方向上具有第一厚度,并且该第一厚度是从第一间隔件结构的外表面的最外点到第一侧壁测量的。P型金属氧化物半导体(PMOS)晶体管包括第二栅极和第二间隔件结构,第二间隔件结构沿第 |
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N型金属氧化物半导体(NMOS)晶体管包括第一栅极和沿第一方向设置在第一栅极的第一侧壁上的第一间隔件结构。第一间隔件结构在第一方向上具有第一厚度,并且该第一厚度是从第一间隔件结构的外表面的最外点到第一侧壁测量的。P型金属氧化物半导体(PMOS)晶体管包括第二栅极和第二间隔件结构,第二间隔件结构沿第</description><language>chi ; eng</language><subject>ELECTRICITY</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210827&DB=EPODOC&CC=CN&NR=113314536A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210827&DB=EPODOC&CC=CN&NR=113314536A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LIN JIANLONG</creatorcontrib><creatorcontrib>LIN SHIHAO</creatorcontrib><creatorcontrib>LIN JIANZHI</creatorcontrib><creatorcontrib>YANG ZHIQUAN</creatorcontrib><creatorcontrib>SU XINWEN</creatorcontrib><title>Semiconductor device and method of making the same</title><description>An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.
N型金属氧化物半导体(NMOS)晶体管包括第一栅极和沿第一方向设置在第一栅极的第一侧壁上的第一间隔件结构。第一间隔件结构在第一方向上具有第一厚度,并且该第一厚度是从第一间隔件结构的外表面的最外点到第一侧壁测量的。P型金属氧化物半导体(PMOS)晶体管包括第二栅极和第二间隔件结构,第二间隔件结构沿第</description><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAKTs3NTM7PSylNLskvUkhJLctMTlVIzEtRyE0tychPUchPU8hNzM7MS1coyUhVKE7MTeVhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfHOfoaGxsaGJqbGZo7GxKgBAKm3K6U</recordid><startdate>20210827</startdate><enddate>20210827</enddate><creator>LIN JIANLONG</creator><creator>LIN SHIHAO</creator><creator>LIN JIANZHI</creator><creator>YANG ZHIQUAN</creator><creator>SU XINWEN</creator><scope>EVB</scope></search><sort><creationdate>20210827</creationdate><title>Semiconductor device and method of making the same</title><author>LIN JIANLONG ; LIN SHIHAO ; LIN JIANZHI ; YANG ZHIQUAN ; SU XINWEN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN113314536A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2021</creationdate><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>LIN JIANLONG</creatorcontrib><creatorcontrib>LIN SHIHAO</creatorcontrib><creatorcontrib>LIN JIANZHI</creatorcontrib><creatorcontrib>YANG ZHIQUAN</creatorcontrib><creatorcontrib>SU XINWEN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LIN JIANLONG</au><au>LIN SHIHAO</au><au>LIN JIANZHI</au><au>YANG ZHIQUAN</au><au>SU XINWEN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor device and method of making the same</title><date>2021-08-27</date><risdate>2021</risdate><abstract>An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.
N型金属氧化物半导体(NMOS)晶体管包括第一栅极和沿第一方向设置在第一栅极的第一侧壁上的第一间隔件结构。第一间隔件结构在第一方向上具有第一厚度,并且该第一厚度是从第一间隔件结构的外表面的最外点到第一侧壁测量的。P型金属氧化物半导体(PMOS)晶体管包括第二栅极和第二间隔件结构,第二间隔件结构沿第</abstract><oa>free_for_read</oa></addata></record> |
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subjects | ELECTRICITY |
title | Semiconductor device and method of making the same |
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