Fixed point FFT implementation architecture with optimized resource consumption

A fixed-point FFT implementation architecture with optimized resource consumption comprises log2 N-level butterfly operation modules and storage modules thereof, butterfly operation of each level is achieved through cooperation of the corresponding butterfly operation module and the corresponding storage module, the butterfly operation module of each level calculates all secondary butterfly operation of the level, and the log2 N-level butterfly operation modules and the storage modules of the log2 N-level butterfly operation modules are used for storing all the secondary butterfly operation of the level. On the basis, when continuous input sequences are processed through assembly line insertion, the calculation period of the whole processor is greatly shortened. On the basis of optimization of the number of operation units and a butterfly operation framework, the word length of each level of butterfly operation is reduced as much as possible through a radix-2 FFT algorithm under the conditions that the symmet