Chip packaging module

Chip packaging module

The invention relates to a chip packaging module. The chip package module includes a package substrate, a chip, and a conductive connection assembly. The chip is disposed on the package substrate. The chip has a first surface and a second surface opposite to the first surface. The first surface is d...

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Hauptverfasser: ZHONG SHENGFENG, ZHU ZHENGLUN
Format: Patent
Sprache:chi ; eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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ZHU ZHENGLUN
description The invention relates to a chip packaging module. The chip package module includes a package substrate, a chip, and a conductive connection assembly. The chip is disposed on the package substrate. The chip has a first surface and a second surface opposite to the first surface. The first surface is divided into a first area, a second area and a third area. The second area is located between the first area and the third area. The chip comprises a flip chip bonding pad group, a lead combination bonding pad group and a signal bonding pad group. The flip chip pad group is located in the first area, the lead bonding pad group is located in the third area, and the signal pad group is located in the second area. The conductive connection assembly is electrically connected between the chip and the package substrate. One of the flip chip pad group and the lead bonding pad group is electrically and physically connected with the conductive connection assembly, and the other is not physically connected with the conductive
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN112736053A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN112736053A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN112736053A3</originalsourceid><addsrcrecordid>eNrjZBB1zsgsUChITM5OTM_MS1fIzU8pzUnlYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxUDlqXmpJfHOfoaGRubGZgamxo7GxKgBAF7nIOM</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Chip packaging module</title><source>esp@cenet</source><creator>ZHONG SHENGFENG ; ZHU ZHENGLUN</creator><creatorcontrib>ZHONG SHENGFENG ; ZHU ZHENGLUN</creatorcontrib><description>The invention relates to a chip packaging module. The chip package module includes a package substrate, a chip, and a conductive connection assembly. The chip is disposed on the package substrate. The chip has a first surface and a second surface opposite to the first surface. The first surface is divided into a first area, a second area and a third area. The second area is located between the first area and the third area. The chip comprises a flip chip bonding pad group, a lead combination bonding pad group and a signal bonding pad group. The flip chip pad group is located in the first area, the lead bonding pad group is located in the third area, and the signal pad group is located in the second area. The conductive connection assembly is electrically connected between the chip and the package substrate. One of the flip chip pad group and the lead bonding pad group is electrically and physically connected with the conductive connection assembly, and the other is not physically connected with the conductive</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210430&amp;DB=EPODOC&amp;CC=CN&amp;NR=112736053A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210430&amp;DB=EPODOC&amp;CC=CN&amp;NR=112736053A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ZHONG SHENGFENG</creatorcontrib><creatorcontrib>ZHU ZHENGLUN</creatorcontrib><title>Chip packaging module</title><description>The invention relates to a chip packaging module. The chip package module includes a package substrate, a chip, and a conductive connection assembly. The chip is disposed on the package substrate. The chip has a first surface and a second surface opposite to the first surface. The first surface is divided into a first area, a second area and a third area. The second area is located between the first area and the third area. The chip comprises a flip chip bonding pad group, a lead combination bonding pad group and a signal bonding pad group. The flip chip pad group is located in the first area, the lead bonding pad group is located in the third area, and the signal pad group is located in the second area. The conductive connection assembly is electrically connected between the chip and the package substrate. One of the flip chip pad group and the lead bonding pad group is electrically and physically connected with the conductive connection assembly, and the other is not physically connected with the conductive</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBB1zsgsUChITM5OTM_MS1fIzU8pzUnlYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxUDlqXmpJfHOfoaGRubGZgamxo7GxKgBAF7nIOM</recordid><startdate>20210430</startdate><enddate>20210430</enddate><creator>ZHONG SHENGFENG</creator><creator>ZHU ZHENGLUN</creator><scope>EVB</scope></search><sort><creationdate>20210430</creationdate><title>Chip packaging module</title><author>ZHONG SHENGFENG ; ZHU ZHENGLUN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN112736053A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>ZHONG SHENGFENG</creatorcontrib><creatorcontrib>ZHU ZHENGLUN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ZHONG SHENGFENG</au><au>ZHU ZHENGLUN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Chip packaging module</title><date>2021-04-30</date><risdate>2021</risdate><abstract>The invention relates to a chip packaging module. The chip package module includes a package substrate, a chip, and a conductive connection assembly. The chip is disposed on the package substrate. The chip has a first surface and a second surface opposite to the first surface. The first surface is divided into a first area, a second area and a third area. The second area is located between the first area and the third area. The chip comprises a flip chip bonding pad group, a lead combination bonding pad group and a signal bonding pad group. The flip chip pad group is located in the first area, the lead bonding pad group is located in the third area, and the signal pad group is located in the second area. The conductive connection assembly is electrically connected between the chip and the package substrate. One of the flip chip pad group and the lead bonding pad group is electrically and physically connected with the conductive connection assembly, and the other is not physically connected with the conductive</abstract><oa>free_for_read</oa></addata></record>
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language chi ; eng
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Chip packaging module
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-25T22%3A50%3A52IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=ZHONG%20SHENGFENG&rft.date=2021-04-30&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN112736053A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true