Cross-clock-domain register read-write circuit and method

The invention provides a cross-clock-domain register read-write circuit and method, and the circuit comprises: a register reading circuit which is connected between a register of a slow clock domain and a bus interface of a fast clock domain, and is used for caching the data in the target register at multiple levels whena target register is selected in a bus to carry out the reading operation, comparing the cached data with the original data, and notifying the bus of reading the data when the cached data is equal to the original data; and a write register circuit which is connected between the register of the low-speed clock domain and the bus interface of the high-speed clock domain, and is used for latching the write data line of the bus and writing data into the target register when the bus selects the target register to perform write operation. According to the circuit and the method, a confirmation mechanism of caching target register data at multiple levels and comparing the target register data with or