METHOD, APPARATUS, AND SYSTEM FOR REDUCING PIPELINE STALLS DUE TO ADDRESS TRANSLATION MISSES

A method, apparatus, and system for reducing pipeline stalls due to address translation misses is presented. An apparatus comprises a memory access instruction pipeline, a translation backup buffer coupled to the memory access instruction pipeline, and a TLB miss queue coupled to both the TLB and the memory access instruction pipeline. The TLB miss queue is configured to selectively store a first memory access instruction that has been removed from the memory access instruction pipeline as a result of the first memory access instruction missing in the TLB along with information associated with the first memory access instruction. The TLB miss queue is further configured to reintroduce the first memory access instruction to the memory access instruction pipeline associated with a return of an address translation related to the first memory access instruction. 提出了一种用于减少由于地址转换缺失引起的管线暂缓的方法、装置和系统。一种装置包括：存储器访问指令管线，耦合到存储器访问指令管线的转换后备缓冲器，以及耦合到TLB和存储器访问指令管线两者的TLB缺失队列。TLB缺失队列被配置为选择性地存储第一存储器访问指令连同与第一存储器访问指令相关联的信息，由于第一存储器