UDP/IP protocol stack implementation method based on FPGA and FPGA chip

UDP/IP protocol stack implementation method based on FPGA and FPGA chip

The invention provides a UDP/IP protocol stack implementation method based on FPGA and an FPGA chip, and the method comprises the steps: defining a UDP/IP protocol stack on the FPGA chip, wherein the protocol stack comprises a UDP transmitting module, a UDP receiving module, an IP transmitting modul...

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Hauptverfasser: FENG SHUANGJI, YANG WEIXIN, CHEN SIMIN, XU ZHIWANG, YIN YEHONG
Format: Patent
Sprache:chi ; eng
Schlagworte:
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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creator FENG SHUANGJI
YANG WEIXIN
CHEN SIMIN
XU ZHIWANG
YIN YEHONG
description The invention provides a UDP/IP protocol stack implementation method based on FPGA and an FPGA chip, and the method comprises the steps: defining a UDP/IP protocol stack on the FPGA chip, wherein the protocol stack comprises a UDP transmitting module, a UDP receiving module, an IP transmitting module and an IP receiving module; carrying out the UDP protocol packaging on external input data through the UDP sending module, sending a packaged data packet to the IP sending module, enabling the IP sending module to receive the sent data, carrying out packaging operation on the received data and then sending the packaged data to the MAC layer; enabling the IP receiving module to receive the IP data packet from the MAC layer, analyzing the IP data packet to obtain a UDP data packet and forwarding the UDP data packet to the UDP receiving module; enabling the UDP receiving module to receive the UDP data packet from the IP receiving module, analyzing the UDP data packet, and storing the analyzed data in a storage area
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN112637075A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN112637075A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN112637075A3</originalsourceid><addsrcrecordid>eNrjZHAPdQnQ9wxQKCjKL8lPzs9RKC5JTM5WyMwtyEnNTc0rSSzJzM9TyE0tychPUUhKLE5NUQDy3QLcHRUS81IgjOSMzAIeBta0xJziVF4ozc2g6OYa4uyhm1qQH59aXJCYnJqXWhLv7GdoaGRmbG5gbupoTIwaAJEQMf0</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>UDP/IP protocol stack implementation method based on FPGA and FPGA chip</title><source>esp@cenet</source><creator>FENG SHUANGJI ; YANG WEIXIN ; CHEN SIMIN ; XU ZHIWANG ; YIN YEHONG</creator><creatorcontrib>FENG SHUANGJI ; YANG WEIXIN ; CHEN SIMIN ; XU ZHIWANG ; YIN YEHONG</creatorcontrib><description>The invention provides a UDP/IP protocol stack implementation method based on FPGA and an FPGA chip, and the method comprises the steps: defining a UDP/IP protocol stack on the FPGA chip, wherein the protocol stack comprises a UDP transmitting module, a UDP receiving module, an IP transmitting module and an IP receiving module; carrying out the UDP protocol packaging on external input data through the UDP sending module, sending a packaged data packet to the IP sending module, enabling the IP sending module to receive the sent data, carrying out packaging operation on the received data and then sending the packaged data to the MAC layer; enabling the IP receiving module to receive the IP data packet from the MAC layer, analyzing the IP data packet to obtain a UDP data packet and forwarding the UDP data packet to the UDP receiving module; enabling the UDP receiving module to receive the UDP data packet from the IP receiving module, analyzing the UDP data packet, and storing the analyzed data in a storage area</description><language>chi ; eng</language><subject>ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210409&amp;DB=EPODOC&amp;CC=CN&amp;NR=112637075A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210409&amp;DB=EPODOC&amp;CC=CN&amp;NR=112637075A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>FENG SHUANGJI</creatorcontrib><creatorcontrib>YANG WEIXIN</creatorcontrib><creatorcontrib>CHEN SIMIN</creatorcontrib><creatorcontrib>XU ZHIWANG</creatorcontrib><creatorcontrib>YIN YEHONG</creatorcontrib><title>UDP/IP protocol stack implementation method based on FPGA and FPGA chip</title><description>The invention provides a UDP/IP protocol stack implementation method based on FPGA and an FPGA chip, and the method comprises the steps: defining a UDP/IP protocol stack on the FPGA chip, wherein the protocol stack comprises a UDP transmitting module, a UDP receiving module, an IP transmitting module and an IP receiving module; carrying out the UDP protocol packaging on external input data through the UDP sending module, sending a packaged data packet to the IP sending module, enabling the IP sending module to receive the sent data, carrying out packaging operation on the received data and then sending the packaged data to the MAC layer; enabling the IP receiving module to receive the IP data packet from the MAC layer, analyzing the IP data packet to obtain a UDP data packet and forwarding the UDP data packet to the UDP receiving module; enabling the UDP receiving module to receive the UDP data packet from the IP receiving module, analyzing the UDP data packet, and storing the analyzed data in a storage area</description><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAPdQnQ9wxQKCjKL8lPzs9RKC5JTM5WyMwtyEnNTc0rSSzJzM9TyE0tychPUUhKLE5NUQDy3QLcHRUS81IgjOSMzAIeBta0xJziVF4ozc2g6OYa4uyhm1qQH59aXJCYnJqXWhLv7GdoaGRmbG5gbupoTIwaAJEQMf0</recordid><startdate>20210409</startdate><enddate>20210409</enddate><creator>FENG SHUANGJI</creator><creator>YANG WEIXIN</creator><creator>CHEN SIMIN</creator><creator>XU ZHIWANG</creator><creator>YIN YEHONG</creator><scope>EVB</scope></search><sort><creationdate>20210409</creationdate><title>UDP/IP protocol stack implementation method based on FPGA and FPGA chip</title><author>FENG SHUANGJI ; YANG WEIXIN ; CHEN SIMIN ; XU ZHIWANG ; YIN YEHONG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN112637075A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2021</creationdate><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>FENG SHUANGJI</creatorcontrib><creatorcontrib>YANG WEIXIN</creatorcontrib><creatorcontrib>CHEN SIMIN</creatorcontrib><creatorcontrib>XU ZHIWANG</creatorcontrib><creatorcontrib>YIN YEHONG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>FENG SHUANGJI</au><au>YANG WEIXIN</au><au>CHEN SIMIN</au><au>XU ZHIWANG</au><au>YIN YEHONG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>UDP/IP protocol stack implementation method based on FPGA and FPGA chip</title><date>2021-04-09</date><risdate>2021</risdate><abstract>The invention provides a UDP/IP protocol stack implementation method based on FPGA and an FPGA chip, and the method comprises the steps: defining a UDP/IP protocol stack on the FPGA chip, wherein the protocol stack comprises a UDP transmitting module, a UDP receiving module, an IP transmitting module and an IP receiving module; carrying out the UDP protocol packaging on external input data through the UDP sending module, sending a packaged data packet to the IP sending module, enabling the IP sending module to receive the sent data, carrying out packaging operation on the received data and then sending the packaged data to the MAC layer; enabling the IP receiving module to receive the IP data packet from the MAC layer, analyzing the IP data packet to obtain a UDP data packet and forwarding the UDP data packet to the UDP receiving module; enabling the UDP receiving module to receive the UDP data packet from the IP receiving module, analyzing the UDP data packet, and storing the analyzed data in a storage area</abstract><oa>free_for_read</oa></addata></record>
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subjects ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title UDP/IP protocol stack implementation method based on FPGA and FPGA chip
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-03T07%3A57%3A08IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=FENG%20SHUANGJI&rft.date=2021-04-09&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN112637075A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true