High-speed low-resource binary convolution unit based on FPGA

The invention provides a high-speed low-resource binary convolution unit based on FPGA, and the binary convolution unit comprises a plurality of multiply-add units MA and a plurality of addition trees, wherein the operation realized by the multiply-add units MA is the summation operation of all mult...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	LUO CONGHUI, HUANG WENJIN, ZENG SHIHAO, HUANG YIHUA
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	CALCULATING COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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