High-speed low-resource binary convolution unit based on FPGA

The invention provides a high-speed low-resource binary convolution unit based on FPGA, and the binary convolution unit comprises a plurality of multiply-add units MA and a plurality of addition trees, wherein the operation realized by the multiply-add units MA is the summation operation of all multiply-add unit MA output results completed by the addition trees; the binary convolution unit is used for realizing the following operations: outputting M + [log2 N] bit, wherein N represents the length of the convolution operation, In represents the activation value of the input feature map, Wn represents the binarization weight, the value is 1 or 1 and is respectively represented by single bits 0 and 1, wn represents a single bit, and i represents an integer greater than 0. The binary convolution unit can save lookup table resources and reduce time delay, and has the characteristics of high speed and low resource. 本发明提供一种基于FPGA的高速低资源的二值卷积单元，所述的二值卷积单元包括若干个乘加单元MA，若干个加法树，所述的乘加单元MA所实现的运算为所述的加法树完成所有乘加单元MA输出结果的求和操作；所述的二