GATE STRUCTURE IN SEMICONDUCTOR DEVICE

The invention relates to a gate structure in a semiconductor device. A method includes depositing a high-k gate dielectric layer over a semiconductor fin and along sidewalls of the semiconductor fin.The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer, and performing passivation processing on the high-k gate dielectric layer through then-type work function metal layer. The passivation treatment includes a remote plasma process. The method includes depositing a fill metal over the n-type work function metal layer to form a metal gatestack over the high-k gate dielectric layer. The metal gate stack includes an n-type work function metal layer and a filler metal. 本公开涉及半导体器件中的栅极结构。一种方法包括在半导体鳍上方并沿着半导体鳍的侧壁沉积高k栅极电介质层。该方法还包括在高k栅极电介质层上方沉积n型功函数金属层，并且通过n型功函数金属层对高k栅极电介质层执行钝化处理。钝化处理包括远程等离子体工艺。该方法该包括在n型功函数金属层上方沉积填充金属，以在高k栅极电介质层上方形成金属栅极堆叠。该金属栅极堆叠包括n型功函数金属层和填充金属。