Integrated circuit layout miniaturization method
The invention provides an integrated circuit layout miniaturization method, and belongs to the technical field of integrated circuit manufacturing. The integrated circuit layout miniaturization methodcomprises the following steps of: acquiring an initial layout, combining mutually contacted graphic...
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| creator | XU GONGMING LI WEIYU |
| description | The invention provides an integrated circuit layout miniaturization method, and belongs to the technical field of integrated circuit manufacturing. The integrated circuit layout miniaturization methodcomprises the following steps of: acquiring an initial layout, combining mutually contacted graphic units in the initial layout, and forming a graphic unit group by the combined mutually contacted graphic units; and according to a preset miniaturization scale, carrying out miniaturization processing on the initial layout combined by the graphic units to obtain a miniature layout. The situation that the contacted pattern units are disconnected after the layout is miniaturized can be reduced, and the manufacturing yield of subsequently manufactured integrated circuits is improved.
本发明提供一种集成电路版图微缩方法，属于集成电路制造技术领域。集成电路版图微缩方法，包括：获取初始版图，并对初始版图内相互接触的图形单元进行合并，合并后的相互接触的图形单元构成图形单元组；根据预设微缩比例微缩处理经图形单元合并后的初始版图，以得到微缩版图。能够减少进行版图微缩后出现相接触的图形单元接触断开的情况，提高后续制得的集成电路的制造良率。 |
| format | Patent |
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本发明提供一种集成电路版图微缩方法，属于集成电路制造技术领域。集成电路版图微缩方法，包括：获取初始版图，并对初始版图内相互接触的图形单元进行合并，合并后的相互接触的图形单元构成图形单元组；根据预设微缩比例微缩处理经图形单元合并后的初始版图，以得到微缩版图。能够减少进行版图微缩后出现相接触的图形单元接触断开的情况，提高后续制得的集成电路的制造良率。</description><language>chi ; eng</language><subject>APPARATUS SPECIALLY ADAPTED THEREFOR ; CINEMATOGRAPHY ; ELECTROGRAPHY ; HOLOGRAPHY ; MATERIALS THEREFOR ; ORIGINALS THEREFOR ; PHOTOGRAPHY ; PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES ; PHYSICS</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210122&DB=EPODOC&CC=CN&NR=112255882A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210122&DB=EPODOC&CC=CN&NR=112255882A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>XU GONGMING</creatorcontrib><creatorcontrib>LI WEIYU</creatorcontrib><title>Integrated circuit layout miniaturization method</title><description>The invention provides an integrated circuit layout miniaturization method, and belongs to the technical field of integrated circuit manufacturing. The integrated circuit layout miniaturization methodcomprises the following steps of: acquiring an initial layout, combining mutually contacted graphic units in the initial layout, and forming a graphic unit group by the combined mutually contacted graphic units; and according to a preset miniaturization scale, carrying out miniaturization processing on the initial layout combined by the graphic units to obtain a miniature layout. The situation that the contacted pattern units are disconnected after the layout is miniaturized can be reduced, and the manufacturing yield of subsequently manufactured integrated circuits is improved.
本发明提供一种集成电路版图微缩方法，属于集成电路制造技术领域。集成电路版图微缩方法，包括：获取初始版图，并对初始版图内相互接触的图形单元进行合并，合并后的相互接触的图形单元构成图形单元组；根据预设微缩比例微缩处理经图形单元合并后的初始版图，以得到微缩版图。能够减少进行版图微缩后出现相接触的图形单元接触断开的情况，提高后续制得的集成电路的制造良率。</description><subject>APPARATUS SPECIALLY ADAPTED THEREFOR</subject><subject>CINEMATOGRAPHY</subject><subject>ELECTROGRAPHY</subject><subject>HOLOGRAPHY</subject><subject>MATERIALS THEREFOR</subject><subject>ORIGINALS THEREFOR</subject><subject>PHOTOGRAPHY</subject><subject>PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDDwzCtJTS9KLElNUUjOLEouzSxRyEmszC8tUcjNzMtMLCktyqxKLMnMz1PITS3JyE_hYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxzn6GhkZGpqYWFkaOxsSoAQC3zSwb</recordid><startdate>20210122</startdate><enddate>20210122</enddate><creator>XU GONGMING</creator><creator>LI WEIYU</creator><scope>EVB</scope></search><sort><creationdate>20210122</creationdate><title>Integrated circuit layout miniaturization method</title><author>XU GONGMING ; LI WEIYU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN112255882A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2021</creationdate><topic>APPARATUS SPECIALLY ADAPTED THEREFOR</topic><topic>CINEMATOGRAPHY</topic><topic>ELECTROGRAPHY</topic><topic>HOLOGRAPHY</topic><topic>MATERIALS THEREFOR</topic><topic>ORIGINALS THEREFOR</topic><topic>PHOTOGRAPHY</topic><topic>PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>XU GONGMING</creatorcontrib><creatorcontrib>LI WEIYU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>XU GONGMING</au><au>LI WEIYU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrated circuit layout miniaturization method</title><date>2021-01-22</date><risdate>2021</risdate><abstract>The invention provides an integrated circuit layout miniaturization method, and belongs to the technical field of integrated circuit manufacturing. The integrated circuit layout miniaturization methodcomprises the following steps of: acquiring an initial layout, combining mutually contacted graphic units in the initial layout, and forming a graphic unit group by the combined mutually contacted graphic units; and according to a preset miniaturization scale, carrying out miniaturization processing on the initial layout combined by the graphic units to obtain a miniature layout. The situation that the contacted pattern units are disconnected after the layout is miniaturized can be reduced, and the manufacturing yield of subsequently manufactured integrated circuits is improved.
本发明提供一种集成电路版图微缩方法，属于集成电路制造技术领域。集成电路版图微缩方法，包括：获取初始版图，并对初始版图内相互接触的图形单元进行合并，合并后的相互接触的图形单元构成图形单元组；根据预设微缩比例微缩处理经图形单元合并后的初始版图，以得到微缩版图。能够减少进行版图微缩后出现相接触的图形单元接触断开的情况，提高后续制得的集成电路的制造良率。</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | APPARATUS SPECIALLY ADAPTED THEREFOR CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY MATERIALS THEREFOR ORIGINALS THEREFOR PHOTOGRAPHY PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES PHYSICS |
| title | Integrated circuit layout miniaturization method |
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