Synchronous semiconductor memory device with a write latency control function

A semiconductor memory device for processing data in synchronization with a system clock applied from the exterior includes a circuit for generating a write latency control signal, a circuit for generating one active information enlarged signal from a plurality of active information signals generate...

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Hauptverfasser:	HOOL LEE, CHUROO PARK, SI-YEOL LEE
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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