Layout design method and layout structure of capacitor based on pmos transistor and metal layer
The invention discloses a layout design method and layout structure of a capacitor based on a pmos transistor and a metal layer, and the layout design method comprises the steps: at least one layer ofmetal is stacked above a grid electrode of the pmos transistor serving as a bottom layer capacitor t...
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| creator | LI CHANGMENG WU HANMING SONG XIN |
| description | The invention discloses a layout design method and layout structure of a capacitor based on a pmos transistor and a metal layer, and the layout design method comprises the steps: at least one layer ofmetal is stacked above a grid electrode of the pmos transistor serving as a bottom layer capacitor to form a unit capacitor, wherein the first layer of metal in the at least one layer of metal is arranged above the grid electrode of the pmos tube in an interdigital shape, one end of the first layer of metal is connected to the grid electrode of the pmos tube to form the negative electrode of theunit capacitor, and the other end of the first layer of metal is connected to the source and drain ends of the pmos tube to form the positive electrode of the unit capacitor. According to the invention, the pmos transistor and the metal layer are combined together, and the first layer of metal or multiple layers of metal are added into the original pmos capacitor and stacked together, so that a larger capacitance value can |
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According to the invention, the pmos transistor and the metal layer are combined together, and the first layer of metal or multiple layers of metal are added into the original pmos capacitor and stacked together, so that a larger capacitance value can</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200508&DB=EPODOC&CC=CN&NR=111129004A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200508&DB=EPODOC&CC=CN&NR=111129004A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LI CHANGMENG</creatorcontrib><creatorcontrib>WU HANMING</creatorcontrib><creatorcontrib>SONG XIN</creatorcontrib><title>Layout design method and layout structure of capacitor based on pmos transistor and metal layer</title><description>The invention discloses a layout design method and layout structure of a capacitor based on a pmos transistor and a metal layer, and the layout design method comprises the steps: at least one layer ofmetal is stacked above a grid electrode of the pmos transistor serving as a bottom layer capacitor to form a unit capacitor, wherein the first layer of metal in the at least one layer of metal is arranged above the grid electrode of the pmos tube in an interdigital shape, one end of the first layer of metal is connected to the grid electrode of the pmos tube to form the negative electrode of theunit capacitor, and the other end of the first layer of metal is connected to the source and drain ends of the pmos tube to form the positive electrode of the unit capacitor. According to the invention, the pmos transistor and the metal layer are combined together, and the first layer of metal or multiple layers of metal are added into the original pmos capacitor and stacked together, so that a larger capacitance value can</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjDsOwjAQRN1QIOAOywGQwqehRBGIAlHRW0u8IZYcr-VdF9yeWHAAppnizby5sTd8c1FwJP4VYSQd2AFGB-ELRHPptGQC7qHDhJ1XzvBEIQccIY0soBmjeKmgXicLhiqgvDSzHoPQ6tcLs76cH-11Q4ktyaSjSGrb-3bK7tg0h9P-n80Hm2c9CQ</recordid><startdate>20200508</startdate><enddate>20200508</enddate><creator>LI CHANGMENG</creator><creator>WU HANMING</creator><creator>SONG XIN</creator><scope>EVB</scope></search><sort><creationdate>20200508</creationdate><title>Layout design method and layout structure of capacitor based on pmos transistor and metal layer</title><author>LI CHANGMENG ; WU HANMING ; SONG XIN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN111129004A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LI CHANGMENG</creatorcontrib><creatorcontrib>WU HANMING</creatorcontrib><creatorcontrib>SONG XIN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LI CHANGMENG</au><au>WU HANMING</au><au>SONG XIN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Layout design method and layout structure of capacitor based on pmos transistor and metal layer</title><date>2020-05-08</date><risdate>2020</risdate><abstract>The invention discloses a layout design method and layout structure of a capacitor based on a pmos transistor and a metal layer, and the layout design method comprises the steps: at least one layer ofmetal is stacked above a grid electrode of the pmos transistor serving as a bottom layer capacitor to form a unit capacitor, wherein the first layer of metal in the at least one layer of metal is arranged above the grid electrode of the pmos tube in an interdigital shape, one end of the first layer of metal is connected to the grid electrode of the pmos tube to form the negative electrode of theunit capacitor, and the other end of the first layer of metal is connected to the source and drain ends of the pmos tube to form the positive electrode of the unit capacitor. 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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Layout design method and layout structure of capacitor based on pmos transistor and metal layer |
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