MECHANISM TO ENTER OR EXIT RETENTION LEVEL VOLTAGE WHILE A SYSTEM-ON-A-CHIP IS IN LOW POWER MODE

A computing device, system and method. The computing device includes a memory storing instructions, and a processing circuitry coupled to the memory. The processing circuitry is configured to executethe instructions to process a first control signal and a second control signal from respective first and second control pins of a computing platform. The processing circuitry is further to transitionthe computing platform, based on a combination of the first control signal and the second control signal and using at least one voltage pin on the platform, between a low power state and a retention power state without transitioning to an operational power state in between. 本发明公开了一种计算设备、系统和方法。该计算设备包括存储指令的存储器以及耦接到存储器的处理电路，该处理电路被配置为执行指令以处理来自计算平台的相应的第一控制引脚和第二控制引脚的第一控制信号和第二控制信号。处理电路还用于基于第一控制信号和第二控制信号的组合并使用平台上的至少一个电压引脚，进一步使计算平台在低功率状态和保持功率状态之间转换，而不在其间转换到工作功率状态。