MEMORY GATE DRIVER TECHNOLOGY FOR FLASH MEMORY CELLS

A memory array including a first memory cell including a first memory gate coupled to receive a first signal. The memory array including a second memory cell including a first memory gate coupled to receive a second signal. The magnitude of the second signal is different than the magnitude of the first signal. The memory array including a third memory cell including a first memory gate coupled toreceive a third signal. The magnitude of the third signal is different than the magnitude of the first signal and the magnitude of the second signal. The first signal, the second signal and the thirdsignal are received concurrently. 一种存储阵列，其包括第一存储单元，该第一存储单元包括被耦合以接收第一信号的第一存储栅极。存储阵列包括第二存储单元，该第二存储单元包括被耦合以接收第二信号的第一存储栅极。第二信号的幅度不同于第一信号的幅度。存储阵列包括第三存储单元，该第三存储单元包括被耦合以接收第三信号的第一存储栅极。第三信号的幅度不同于第一信号的幅度和第二信号的幅度。第一信号、第二信号和第三信号被同时接收。