Integrated chip and forming method thereof

Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip co...

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Hauptverfasser: HUANG WEN-TUO, LIN CHIA-SHENG, LIU PO-WEI, LI PINGNG, HSU YU-LING, SHIH HUNG-LING, YANG SHIH KUANG, TSAIR YONG-SHIUAN
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creator HUANG WEN-TUO
LIN CHIA-SHENG
LIU PO-WEI
LI PINGNG
HSU YU-LING
SHIH HUNG-LING
YANG SHIH KUANG
TSAIR YONG-SHIUAN
description Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along alength of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length ofthe word line and underlies the word line. An embodiment of the invention also relates to an integrated chip and a forming method thereof. 本申请的各个实施例涉及一种集成存储器芯片,集成存储器芯片具有用于减小漏电流的增强的器件区布局和扩大的字线蚀刻工艺窗口(例如,增强的字线蚀刻弹性)。在一些实施例中,集成存储器芯
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In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along alength of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length ofthe word line and underlies the word line. An embodiment of the invention also relates to an integrated chip and a forming method thereof. 本申请的各个实施例涉及一种集成存储器芯片,集成存储器芯片具有用于减小漏电流的增强的器件区布局和扩大的字线蚀刻工艺窗口(例如,增强的字线蚀刻弹性)。在一些实施例中,集成存储器芯</description><language>chi ; eng</language><subject>ELECTRICITY</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200403&amp;DB=EPODOC&amp;CC=CN&amp;NR=110957323A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200403&amp;DB=EPODOC&amp;CC=CN&amp;NR=110957323A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HUANG WEN-TUO</creatorcontrib><creatorcontrib>LIN CHIA-SHENG</creatorcontrib><creatorcontrib>LIU PO-WEI</creatorcontrib><creatorcontrib>LI PINGNG</creatorcontrib><creatorcontrib>HSU YU-LING</creatorcontrib><creatorcontrib>SHIH HUNG-LING</creatorcontrib><creatorcontrib>YANG SHIH KUANG</creatorcontrib><creatorcontrib>TSAIR YONG-SHIUAN</creatorcontrib><title>Integrated chip and forming method thereof</title><description>Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). 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title Integrated chip and forming method thereof
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