Structure of novel DRAM integrated circuit

The invention discloses a structure of a novel DRAM integrated circuit, and relates to an integrated circuit technology and a semiconductor technology. Based on a novel longitudinal columnar TMOS device structure, an N+ doped substrate and an N-epitaxial layer are arranged at the lowermost layer to serve as a drain electrode. A P epitaxial layer is arranged in the middle to serve as a grid electrode channel. An N+ germanium-silicon epitaxial layer is arranged at the uppermost layer to serve as a source electrode. The outer ring of the columnar structure is surrounded by an oxide layer, whereinthree surfaces are covered by a polycrystalline silicon layer as a grid electrode, and the rest surface is covered by a metal layer to form a capacitor with the drain electrode of a MOS transistor. The polycrystalline silicon is provided with a lead hole for connecting a word line. Another lead hole is formed in the germanium-silicon layer and is connected with a bit line. According to the key technical problem to be sol