Synchronous multi-thread processor

A synchronous multi-thread processor comprises an index RAM (random access memory), a storage buffer, a data cache and at least two assembly lines; the at least two assembly lines are respectively connected with the index RAM, the storage buffer and the data cache and are suitable for accessing the...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: YE ZHENGGUO, AN WUMU, YANG LIUXI, HUA SHAOXIONG, JI ZHONGLIANG, CAO XIAOLUN, YE CHAO, LIU PEIJUN, LIU XINCHAO
Format: Patent
Sprache:chi ; eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator YE ZHENGGUO
AN WUMU
YANG LIUXI
HUA SHAOXIONG
JI ZHONGLIANG
CAO XIAOLUN
YE CHAO
LIU PEIJUN
LIU XINCHAO
description A synchronous multi-thread processor comprises an index RAM (random access memory), a storage buffer, a data cache and at least two assembly lines; the at least two assembly lines are respectively connected with the index RAM, the storage buffer and the data cache and are suitable for accessing the data cache. Each assembly line corresponds to an independent thread, at least one assembly line is an interruptible assembly line, at least one assembly line is a non-interruptible assembly line, and the interruptible assembly line is suitable for stopping a currently executed non-data storage instruction when a data storage instruction is received and executing the data storage instruction. According to the scheme, the data storage operation can be carried out in real time. 一种同步多线程处理器,包括:索引RAM、存储缓存器、数据高速缓存器以及至少两条流水线,其中:所述至少两条流水线,分别与所述索引RAM、所述存储缓存器以及所述数据高速缓存器均连接,适于访问所述数据高速缓存器;每一条流水线对应一个独立的线程,且至少一条流水线为可中断流水线,至少一条流水线为非可中断流水线,其中:所述可中断流水线适于在接收到数据存储指令时停止当前所执行的非数据存储指令,并执行所述数据存储指令。上述方案能够实现实时地进行数据存储操作。
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN110647357A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN110647357A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN110647357A3</originalsourceid><addsrcrecordid>eNrjZFAKrsxLzijKz8svLVbILc0pydQtyShKTUxRKCjKT04tLs4v4mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8c5-hoYGZibmxqbmjsbEqAEA9BImqA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Synchronous multi-thread processor</title><source>esp@cenet</source><creator>YE ZHENGGUO ; AN WUMU ; YANG LIUXI ; HUA SHAOXIONG ; JI ZHONGLIANG ; CAO XIAOLUN ; YE CHAO ; LIU PEIJUN ; LIU XINCHAO</creator><creatorcontrib>YE ZHENGGUO ; AN WUMU ; YANG LIUXI ; HUA SHAOXIONG ; JI ZHONGLIANG ; CAO XIAOLUN ; YE CHAO ; LIU PEIJUN ; LIU XINCHAO</creatorcontrib><description>A synchronous multi-thread processor comprises an index RAM (random access memory), a storage buffer, a data cache and at least two assembly lines; the at least two assembly lines are respectively connected with the index RAM, the storage buffer and the data cache and are suitable for accessing the data cache. Each assembly line corresponds to an independent thread, at least one assembly line is an interruptible assembly line, at least one assembly line is a non-interruptible assembly line, and the interruptible assembly line is suitable for stopping a currently executed non-data storage instruction when a data storage instruction is received and executing the data storage instruction. According to the scheme, the data storage operation can be carried out in real time. 一种同步多线程处理器,包括:索引RAM、存储缓存器、数据高速缓存器以及至少两条流水线,其中:所述至少两条流水线,分别与所述索引RAM、所述存储缓存器以及所述数据高速缓存器均连接,适于访问所述数据高速缓存器;每一条流水线对应一个独立的线程,且至少一条流水线为可中断流水线,至少一条流水线为非可中断流水线,其中:所述可中断流水线适于在接收到数据存储指令时停止当前所执行的非数据存储指令,并执行所述数据存储指令。上述方案能够实现实时地进行数据存储操作。</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200103&amp;DB=EPODOC&amp;CC=CN&amp;NR=110647357A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200103&amp;DB=EPODOC&amp;CC=CN&amp;NR=110647357A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YE ZHENGGUO</creatorcontrib><creatorcontrib>AN WUMU</creatorcontrib><creatorcontrib>YANG LIUXI</creatorcontrib><creatorcontrib>HUA SHAOXIONG</creatorcontrib><creatorcontrib>JI ZHONGLIANG</creatorcontrib><creatorcontrib>CAO XIAOLUN</creatorcontrib><creatorcontrib>YE CHAO</creatorcontrib><creatorcontrib>LIU PEIJUN</creatorcontrib><creatorcontrib>LIU XINCHAO</creatorcontrib><title>Synchronous multi-thread processor</title><description>A synchronous multi-thread processor comprises an index RAM (random access memory), a storage buffer, a data cache and at least two assembly lines; the at least two assembly lines are respectively connected with the index RAM, the storage buffer and the data cache and are suitable for accessing the data cache. Each assembly line corresponds to an independent thread, at least one assembly line is an interruptible assembly line, at least one assembly line is a non-interruptible assembly line, and the interruptible assembly line is suitable for stopping a currently executed non-data storage instruction when a data storage instruction is received and executing the data storage instruction. According to the scheme, the data storage operation can be carried out in real time. 一种同步多线程处理器,包括:索引RAM、存储缓存器、数据高速缓存器以及至少两条流水线,其中:所述至少两条流水线,分别与所述索引RAM、所述存储缓存器以及所述数据高速缓存器均连接,适于访问所述数据高速缓存器;每一条流水线对应一个独立的线程,且至少一条流水线为可中断流水线,至少一条流水线为非可中断流水线,其中:所述可中断流水线适于在接收到数据存储指令时停止当前所执行的非数据存储指令,并执行所述数据存储指令。上述方案能够实现实时地进行数据存储操作。</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAKrsxLzijKz8svLVbILc0pydQtyShKTUxRKCjKT04tLs4v4mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8c5-hoYGZibmxqbmjsbEqAEA9BImqA</recordid><startdate>20200103</startdate><enddate>20200103</enddate><creator>YE ZHENGGUO</creator><creator>AN WUMU</creator><creator>YANG LIUXI</creator><creator>HUA SHAOXIONG</creator><creator>JI ZHONGLIANG</creator><creator>CAO XIAOLUN</creator><creator>YE CHAO</creator><creator>LIU PEIJUN</creator><creator>LIU XINCHAO</creator><scope>EVB</scope></search><sort><creationdate>20200103</creationdate><title>Synchronous multi-thread processor</title><author>YE ZHENGGUO ; AN WUMU ; YANG LIUXI ; HUA SHAOXIONG ; JI ZHONGLIANG ; CAO XIAOLUN ; YE CHAO ; LIU PEIJUN ; LIU XINCHAO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN110647357A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2020</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>YE ZHENGGUO</creatorcontrib><creatorcontrib>AN WUMU</creatorcontrib><creatorcontrib>YANG LIUXI</creatorcontrib><creatorcontrib>HUA SHAOXIONG</creatorcontrib><creatorcontrib>JI ZHONGLIANG</creatorcontrib><creatorcontrib>CAO XIAOLUN</creatorcontrib><creatorcontrib>YE CHAO</creatorcontrib><creatorcontrib>LIU PEIJUN</creatorcontrib><creatorcontrib>LIU XINCHAO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YE ZHENGGUO</au><au>AN WUMU</au><au>YANG LIUXI</au><au>HUA SHAOXIONG</au><au>JI ZHONGLIANG</au><au>CAO XIAOLUN</au><au>YE CHAO</au><au>LIU PEIJUN</au><au>LIU XINCHAO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Synchronous multi-thread processor</title><date>2020-01-03</date><risdate>2020</risdate><abstract>A synchronous multi-thread processor comprises an index RAM (random access memory), a storage buffer, a data cache and at least two assembly lines; the at least two assembly lines are respectively connected with the index RAM, the storage buffer and the data cache and are suitable for accessing the data cache. Each assembly line corresponds to an independent thread, at least one assembly line is an interruptible assembly line, at least one assembly line is a non-interruptible assembly line, and the interruptible assembly line is suitable for stopping a currently executed non-data storage instruction when a data storage instruction is received and executing the data storage instruction. According to the scheme, the data storage operation can be carried out in real time. 一种同步多线程处理器,包括:索引RAM、存储缓存器、数据高速缓存器以及至少两条流水线,其中:所述至少两条流水线,分别与所述索引RAM、所述存储缓存器以及所述数据高速缓存器均连接,适于访问所述数据高速缓存器;每一条流水线对应一个独立的线程,且至少一条流水线为可中断流水线,至少一条流水线为非可中断流水线,其中:所述可中断流水线适于在接收到数据存储指令时停止当前所执行的非数据存储指令,并执行所述数据存储指令。上述方案能够实现实时地进行数据存储操作。</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language chi ; eng
recordid cdi_epo_espacenet_CN110647357A
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Synchronous multi-thread processor
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-21T14%3A28%3A47IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=YE%20ZHENGGUO&rft.date=2020-01-03&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN110647357A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true