HARDWARE-ASSISTED PAGING MECHANISM

The present invention relates to a hardware-assisted paging mechanism. The processing circuitry for computer memory management includes memory reduction circuitry to implement a memory reduction technique; and reference count information collection circuitry to: access a memory region, the memory region subject to the memory reduction technique; obtain an indication of memory reduction of the memory region; calculate metrics based on the indication of memory reduction of cache lines associated with the memory region; and provide the metrics to a system software component for use in memory management mechanisms. 本公开涉及硬件辅助的页面调度机制。用于计算机存储器管理的处理电路包括：存储器减小电路，要实现存储器减小技术；以及引用计数信息采集电路，要：访问存储器区，所述存储器区受制于所述存储器减小技术；获得所述存储器区的存储器减小的指示；计算基于与所述存储器区相关联的高速缓存线的存储器减小的指示的度量；以及将所述度量提供给系统软件组件以用于在存储器管理机制中使用。