SRAM write operation tracking circuit

An SRAM write operation tracking circuit includes: an analog memory cell circuit coupled to a compensation circuit and adapted to simulate an SRAM memory cell; a compensation circuit, wherein the input end of the compensation circuit is coupled with the output end of an internal storage node of the analog storage unit circuit, and the output end of the compensation circuit is coupled with the clock generation circuit, and the compensation circuit is suitable for compensating the output voltage of the output end of the internal storage node of the analog storage unit circuit so as to prolong the time delay of the output voltage of the output end of the internal storage node jumping from a high level to a low level. According to the scheme, the starting time of the write tracking circuit canbe prolonged, and the situation that the write circuit cannot write normally is avoided. 一种SRAM写操作追踪电路，包括：模拟存储单元电路，与补偿电路耦接，适于模拟SRAM存储单元；补偿电路，输入端与所述模拟存储单元电路的内部存储节点输出端耦接，输出端与时钟产生电路耦接，适于对所述模拟存储单元电路的内部存储节点输出端的输出电压进行补偿，以增加所述内部存储节