INSTRUCTION SET ARCHITECTURE TO FACILITATE ENERGY-EFFICIENT COMPUTING FOR EXASCALE ARCHITECTURES

Disclosed embodiments relate to an instruction set architecture to facilitate energy-efficient computing for exascale architectures. In one embodiment, a processor includes a plurality of acceleratorcores, each having a corresponding instruction set architecture (ISA); a fetch circuit to fetch one o...

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Hauptverfasser:	SURESH PRIYANKA, JAIN SAMKIT, HOWARD JASON M, MORE ANKIT, NAGASUNDARAM BANU MEENAKSHI, DAKSHINAMOORTHY SRIKANTH, GRIFFIN WILLIAM PAUL, PAWLOWSKI ROBERT, SOMASEKHAR DINESH, FRYMAN JOSHUA B, SEEGEHALLI AVINASH M, GANEV IVAN B, DUNNING DAVID S, BHADVIYA BHAVITAVYA B, YEOLEKAR PRANAV, KHARE SURHUD, CLEDAT ROMAIN E
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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