INSTRUCTION SET ARCHITECTURE TO FACILITATE ENERGY-EFFICIENT COMPUTING FOR EXASCALE ARCHITECTURES

Disclosed embodiments relate to an instruction set architecture to facilitate energy-efficient computing for exascale architectures. In one embodiment, a processor includes a plurality of acceleratorcores, each having a corresponding instruction set architecture (ISA); a fetch circuit to fetch one or more instructions specifying one of the accelerator cores, a decode circuit to decode the one ormore fetched instructions, and an issue circuit to translate the one or more decoded instructions into the ISA corresponding to the specified accelerator core, collate the one or more translated instructions into an instruction packet, and issue the instruction packet to the specified accelerator core; and, wherein the plurality of accelerator cores comprise a memory engine (MENG), a collective engine (CENG), a queue engine (QENG), and a chain management unit (CMU). 所公开的实施例涉及用于促进用于百亿亿次级架构的高能效计算的指令集架构。在一个实施例中，处理器包括：多个加速器核，每个加速器核都具有对应的指令集架构(ISA)；取出电路，用于取出指定加速器核中的一个加速器核的一条或多条指令；解码电路，用于对一条或多条取出的指令解码；以及发布电路，用于：将一条或多条经解码的指令转