BIST and ECC combined memory detection method in system chip

The invention discloses a BIST and ECC combined memory detection method in a system chip, and belongs to the field of built-in self-test of memories. A BIST module, an ECC module and a memory are included, the method specifically comprises the following steps that when an ECC module detects that data written into a read-out memory is inconsistent with data written into the read-out memory and only one bit of error data exists, an ECC correction algorithm is called to correct the one bit of error, then the data is returned to the BIST module, and the BIST module gives a correct result; when the ECC module does not detect an error, a result signal at the BIST can give a correct result; if two or more bits of errors exist, the ECC is not corrected, when the errors are returned to the BIST, wrong data can be detected, and the BIST can give an error result feedback. According to the invention, the detected yield of the memory is improved, and the memory is still considered to be correct when one bit error occurs i