Inverse transport processor with memory address circuitry

Inverse transport processor with memory address circuitry

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: M.S. DEISS, K.E. BRIDGEWATER
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
PICTORIAL COMMUNICATION, e.g. TELEVISION
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator M.S. DEISS
K.E. BRIDGEWATER
description
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN1100438CC</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN1100438CC</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN1100438CC3</originalsourceid><addsrcrecordid>eNrjZLD0zCtLLSpOVSgpSswrLsgvKlEoKMpPTi0uzi9SKM8syVDITc3NL6pUSExJKQKKKiRnFiWXZpYUVfIwsKYl5hSn8kJpbgYFN9cQZw_d1IL8-NTigsTk1LzUknhnP0NDAwMTYwtnZ2MilAAAVccvTA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Inverse transport processor with memory address circuitry</title><source>esp@cenet</source><creator>M.S. DEISS ; K.E. BRIDGEWATER</creator><creatorcontrib>M.S. DEISS ; K.E. BRIDGEWATER</creatorcontrib><edition>7</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; PICTORIAL COMMUNICATION, e.g. TELEVISION</subject><creationdate>2003</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20030129&amp;DB=EPODOC&amp;CC=CN&amp;NR=1100438C$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20030129&amp;DB=EPODOC&amp;CC=CN&amp;NR=1100438C$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>M.S. DEISS</creatorcontrib><creatorcontrib>K.E. BRIDGEWATER</creatorcontrib><title>Inverse transport processor with memory address circuitry</title><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>PICTORIAL COMMUNICATION, e.g. TELEVISION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2003</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLD0zCtLLSpOVSgpSswrLsgvKlEoKMpPTi0uzi9SKM8syVDITc3NL6pUSExJKQKKKiRnFiWXZpYUVfIwsKYl5hSn8kJpbgYFN9cQZw_d1IL8-NTigsTk1LzUknhnP0NDAwMTYwtnZ2MilAAAVccvTA</recordid><startdate>20030129</startdate><enddate>20030129</enddate><creator>M.S. DEISS</creator><creator>K.E. BRIDGEWATER</creator><scope>EVB</scope></search><sort><creationdate>20030129</creationdate><title>Inverse transport processor with memory address circuitry</title><author>M.S. DEISS ; K.E. BRIDGEWATER</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN1100438CC3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2003</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>PICTORIAL COMMUNICATION, e.g. TELEVISION</topic><toplevel>online_resources</toplevel><creatorcontrib>M.S. DEISS</creatorcontrib><creatorcontrib>K.E. BRIDGEWATER</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>M.S. DEISS</au><au>K.E. BRIDGEWATER</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Inverse transport processor with memory address circuitry</title><date>2003-01-29</date><risdate>2003</risdate><edition>7</edition><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_CN1100438CC
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
PICTORIAL COMMUNICATION, e.g. TELEVISION
title Inverse transport processor with memory address circuitry
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-22T15%3A00%3A01IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=M.S.%20DEISS&rft.date=2003-01-29&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN1100438CC%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true