CHIP SCALE PACKAGE STRUCTURES

The present invention discloses a chip scale package structure. The chip scale package structure includes an image sensor chip and a chip. The image sensor chip includes a first redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the first redistribution layer. The chip includes a second redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the second redistribution layer. The area ofthe chip is smaller than that of the image sensor chip. The second redistribution layer of the chip bonds the first redistribution layer of the image sensor chip. 本发明公开一种晶片级芯片尺寸封装结构，包括：影像感测芯片以及芯片。影像感测芯片包括第一重分布层，其中第一重分布层包含导线与导电衬垫，导电衬垫形成于导线上，且导电衬垫露出于第一重分布层的表面。芯片包括第二重分布层，其中第二重分布层包含导线与导电衬垫，导电衬垫形成于导线上，且导电衬垫露出于第二重分布层的表面。芯片的面积小于影像感测芯片的面积，且芯片通过第二重分布层与影像感测芯片的第一重分布层接合。