Equipment
The embodiment of the invention discloses equipment, and belongs to the technical field of electronics. The equipment comprises a master node and at least one slave node, wherein the master node comprises four master CPUs, a master PCH and a first CPLD, each slave node comprises four slave CPUs and...
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| creator | WU JUNHE LIU PINQIANG |
| description | The embodiment of the invention discloses equipment, and belongs to the technical field of electronics. The equipment comprises a master node and at least one slave node, wherein the master node comprises four master CPUs, a master PCH and a first CPLD, each slave node comprises four slave CPUs and a second CPLD, the first CPLD is electrically connected with the master PCH and the four master CPUs, the second CPLD in each slave node is electrically connected with the four slave CPUs, and the master node is electrically connected with each slave node; the main PCH is used for generating a PMSYNC signal and a first clock signal and sending the PMSYNC signal and the first clock signal to the first CPLD; the first CPLD is used for sending the received PMSYNC signal and the first clock signal to the four main CPUs; the second CPLD is used for receiving the PMSYNC signal generated by the master PCH, obtaining a second clock signal, sending the second clock signal to the four slave CPUs, andsending the PMSYNC signal |
| format | Patent |
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The equipment comprises a master node and at least one slave node, wherein the master node comprises four master CPUs, a master PCH and a first CPLD, each slave node comprises four slave CPUs and a second CPLD, the first CPLD is electrically connected with the master PCH and the four master CPUs, the second CPLD in each slave node is electrically connected with the four slave CPUs, and the master node is electrically connected with each slave node; the main PCH is used for generating a PMSYNC signal and a first clock signal and sending the PMSYNC signal and the first clock signal to the first CPLD; the first CPLD is used for sending the received PMSYNC signal and the first clock signal to the four main CPUs; the second CPLD is used for receiving the PMSYNC signal generated by the master PCH, obtaining a second clock signal, sending the second clock signal to the four slave CPUs, andsending the PMSYNC signal</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190705&DB=EPODOC&CC=CN&NR=109977069A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76294</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190705&DB=EPODOC&CC=CN&NR=109977069A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>WU JUNHE</creatorcontrib><creatorcontrib>LIU PINQIANG</creatorcontrib><title>Equipment</title><description>The embodiment of the invention discloses equipment, and belongs to the technical field of electronics. The equipment comprises a master node and at least one slave node, wherein the master node comprises four master CPUs, a master PCH and a first CPLD, each slave node comprises four slave CPUs and a second CPLD, the first CPLD is electrically connected with the master PCH and the four master CPUs, the second CPLD in each slave node is electrically connected with the four slave CPUs, and the master node is electrically connected with each slave node; the main PCH is used for generating a PMSYNC signal and a first clock signal and sending the PMSYNC signal and the first clock signal to the first CPLD; the first CPLD is used for sending the received PMSYNC signal and the first clock signal to the four main CPUs; the second CPLD is used for receiving the PMSYNC signal generated by the master PCH, obtaining a second clock signal, sending the second clock signal to the four slave CPUs, andsending the PMSYNC signal</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZOB0LSzNLMhNzSvhYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxzn6GBpaW5uYGZpaOxsSoAQCmwBzI</recordid><startdate>20190705</startdate><enddate>20190705</enddate><creator>WU JUNHE</creator><creator>LIU PINQIANG</creator><scope>EVB</scope></search><sort><creationdate>20190705</creationdate><title>Equipment</title><author>WU JUNHE ; LIU PINQIANG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN109977069A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2019</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>WU JUNHE</creatorcontrib><creatorcontrib>LIU PINQIANG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>WU JUNHE</au><au>LIU PINQIANG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Equipment</title><date>2019-07-05</date><risdate>2019</risdate><abstract>The embodiment of the invention discloses equipment, and belongs to the technical field of electronics. The equipment comprises a master node and at least one slave node, wherein the master node comprises four master CPUs, a master PCH and a first CPLD, each slave node comprises four slave CPUs and a second CPLD, the first CPLD is electrically connected with the master PCH and the four master CPUs, the second CPLD in each slave node is electrically connected with the four slave CPUs, and the master node is electrically connected with each slave node; the main PCH is used for generating a PMSYNC signal and a first clock signal and sending the PMSYNC signal and the first clock signal to the first CPLD; the first CPLD is used for sending the received PMSYNC signal and the first clock signal to the four main CPUs; the second CPLD is used for receiving the PMSYNC signal generated by the master PCH, obtaining a second clock signal, sending the second clock signal to the four slave CPUs, andsending the PMSYNC signal</abstract><oa>free_for_read</oa></addata></record> |
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| language | chi ; eng |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Equipment |
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