Wafer-level package with enhanced performance
The present disclosure relates to a packaging process to enhance thermal and electrical performance of a wafer-level package. The wafer-level package with enhanced performance includes a first thinneddie (14) having a first device layer (20), a multilayer redistribution structure (52), a first mold...
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| creator | HAMMOND JONATHAN HALE CHADWICK JON COSTA JULIO C HATCHER MERRILL ALBERT JR VANDEMEER JAN EDWARD |
| description | The present disclosure relates to a packaging process to enhance thermal and electrical performance of a wafer-level package. The wafer-level package with enhanced performance includes a first thinneddie (14) having a first device layer (20), a multilayer redistribution structure (52), a first mold compound (42), and a second mold compound (74). The multilayer redistribution structure includes package contacts on a bottom surface of the multilayer redistribution structure and redistribution interconnects connecting the first device layer to the package contacts. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define a cavity (66) within the first mold compound and over the first thinned die. The second mold compound fills the cavity and is in contact with the top surface of the first thinned die.
本公开涉及一种用于增强晶片级封装的热性能和电气性能的封装工艺。具有增强性能的所述晶片级封装包括具有第一装置层(20)的第一薄化裸片(14)、多层再分布结构(52)、第一模化合物(42) |
| format | Patent |
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本公开涉及一种用于增强晶片级封装的热性能和电气性能的封装工艺。具有增强性能的所述晶片级封装包括具有第一装置层(20)的第一薄化裸片(14)、多层再分布结构(52)、第一模化合物(42)</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190604&DB=EPODOC&CC=CN&NR=109844938A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190604&DB=EPODOC&CC=CN&NR=109844938A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HAMMOND JONATHAN HALE</creatorcontrib><creatorcontrib>CHADWICK JON</creatorcontrib><creatorcontrib>COSTA JULIO C</creatorcontrib><creatorcontrib>HATCHER MERRILL ALBERT JR</creatorcontrib><creatorcontrib>VANDEMEER JAN EDWARD</creatorcontrib><title>Wafer-level package with enhanced performance</title><description>The present disclosure relates to a packaging process to enhance thermal and electrical performance of a wafer-level package. The wafer-level package with enhanced performance includes a first thinneddie (14) having a first device layer (20), a multilayer redistribution structure (52), a first mold compound (42), and a second mold compound (74). The multilayer redistribution structure includes package contacts on a bottom surface of the multilayer redistribution structure and redistribution interconnects connecting the first device layer to the package contacts. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define a cavity (66) within the first mold compound and over the first thinned die. The second mold compound fills the cavity and is in contact with the top surface of the first thinned die.
本公开涉及一种用于增强晶片级封装的热性能和电气性能的封装工艺。具有增强性能的所述晶片级封装包括具有第一装置层(20)的第一薄化裸片(14)、多层再分布结构(52)、第一模化合物(42)</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNANT0xLLdLNSS1LzVEoSEzOTkxPVSjPLMlQSM3LSMxLTk1RKEgtSssvygVxeBhY0xJzilN5oTQ3g6Kba4izh25qQX58ajFQf2peakm8s5-hgaWFiYmlsYWjMTFqAMAbKjo</recordid><startdate>20190604</startdate><enddate>20190604</enddate><creator>HAMMOND JONATHAN HALE</creator><creator>CHADWICK JON</creator><creator>COSTA JULIO C</creator><creator>HATCHER MERRILL ALBERT JR</creator><creator>VANDEMEER JAN EDWARD</creator><scope>EVB</scope></search><sort><creationdate>20190604</creationdate><title>Wafer-level package with enhanced performance</title><author>HAMMOND JONATHAN HALE ; CHADWICK JON ; COSTA JULIO C ; HATCHER MERRILL ALBERT JR ; VANDEMEER JAN EDWARD</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN109844938A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>HAMMOND JONATHAN HALE</creatorcontrib><creatorcontrib>CHADWICK JON</creatorcontrib><creatorcontrib>COSTA JULIO C</creatorcontrib><creatorcontrib>HATCHER MERRILL ALBERT JR</creatorcontrib><creatorcontrib>VANDEMEER JAN EDWARD</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HAMMOND JONATHAN HALE</au><au>CHADWICK JON</au><au>COSTA JULIO C</au><au>HATCHER MERRILL ALBERT JR</au><au>VANDEMEER JAN EDWARD</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Wafer-level package with enhanced performance</title><date>2019-06-04</date><risdate>2019</risdate><abstract>The present disclosure relates to a packaging process to enhance thermal and electrical performance of a wafer-level package. The wafer-level package with enhanced performance includes a first thinneddie (14) having a first device layer (20), a multilayer redistribution structure (52), a first mold compound (42), and a second mold compound (74). The multilayer redistribution structure includes package contacts on a bottom surface of the multilayer redistribution structure and redistribution interconnects connecting the first device layer to the package contacts. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define a cavity (66) within the first mold compound and over the first thinned die. The second mold compound fills the cavity and is in contact with the top surface of the first thinned die.
本公开涉及一种用于增强晶片级封装的热性能和电气性能的封装工艺。具有增强性能的所述晶片级封装包括具有第一装置层(20)的第一薄化裸片(14)、多层再分布结构(52)、第一模化合物(42)</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Wafer-level package with enhanced performance |
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