The invention discloses an HBS chip data receiving compatible circuit

The invention discloses an HBS chip data receiving compatible circuit

The invention discloses an HBS chip data receiving compatible circuit which comprises an HBS chip, and the HBS chip is a first HBS chip or a second HBS chip which packages the same HBS chip. The HBS chip comprises a first receiving data sending pin and a second receiving data sending pin; T. The fir...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: XU PENGYANG, WANG QIUCHEN, ZHAO HUAIJIE, SHI JINGFENG
Format: Patent
Sprache:chi ; eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator XU PENGYANG
WANG QIUCHEN
ZHAO HUAIJIE
SHI JINGFENG
description The invention discloses an HBS chip data receiving compatible circuit which comprises an HBS chip, and the HBS chip is a first HBS chip or a second HBS chip which packages the same HBS chip. The HBS chip comprises a first receiving data sending pin and a second receiving data sending pin; T. The first receiving data sending pin is connected with a first data receiving circuit, and the second receiving data sending pin is connected with a second data receiving circuit; T. The circuit also comprises a second resistor and a first capacitor. W; when the first HBS chip is mounted, the first data receiving circuit is mounted, and the second data receiving circuit is not mounted; W; when the second HBS chip is mounted, the second data receiving circuit is mounted, and the first data receiving circuit is not mounted; T. Through selective mounting of components, two types of HBS chips share a peripheral setting circuit, and the circuit does not need to be adjusted and redesigned according to chip adaptation, so that t
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN109614365A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN109614365A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN109614365A3</originalsourceid><addsrcrecordid>eNqNyjEOgkAQBdBtLIx6h_EAJhKUxFIJhspGejIOX5lknd2wK-e38QBWr3lL13QjSG2GZQ1GgybxISERG7WXO8mokQbOTBMEOqu9SMI7ctaHB4lO8tG8dosn-4TNz5XbXpuubneIoUeKLDDkvr4V-1NVHMrqeC7_OV-4jTLP</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>The invention discloses an HBS chip data receiving compatible circuit</title><source>esp@cenet</source><creator>XU PENGYANG ; WANG QIUCHEN ; ZHAO HUAIJIE ; SHI JINGFENG</creator><creatorcontrib>XU PENGYANG ; WANG QIUCHEN ; ZHAO HUAIJIE ; SHI JINGFENG</creatorcontrib><description>The invention discloses an HBS chip data receiving compatible circuit which comprises an HBS chip, and the HBS chip is a first HBS chip or a second HBS chip which packages the same HBS chip. The HBS chip comprises a first receiving data sending pin and a second receiving data sending pin; T. The first receiving data sending pin is connected with a first data receiving circuit, and the second receiving data sending pin is connected with a second data receiving circuit; T. The circuit also comprises a second resistor and a first capacitor. W; when the first HBS chip is mounted, the first data receiving circuit is mounted, and the second data receiving circuit is not mounted; W; when the second HBS chip is mounted, the second data receiving circuit is mounted, and the first data receiving circuit is not mounted; T. Through selective mounting of components, two types of HBS chips share a peripheral setting circuit, and the circuit does not need to be adjusted and redesigned according to chip adaptation, so that t</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190412&amp;DB=EPODOC&amp;CC=CN&amp;NR=109614365A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190412&amp;DB=EPODOC&amp;CC=CN&amp;NR=109614365A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>XU PENGYANG</creatorcontrib><creatorcontrib>WANG QIUCHEN</creatorcontrib><creatorcontrib>ZHAO HUAIJIE</creatorcontrib><creatorcontrib>SHI JINGFENG</creatorcontrib><title>The invention discloses an HBS chip data receiving compatible circuit</title><description>The invention discloses an HBS chip data receiving compatible circuit which comprises an HBS chip, and the HBS chip is a first HBS chip or a second HBS chip which packages the same HBS chip. The HBS chip comprises a first receiving data sending pin and a second receiving data sending pin; T. The first receiving data sending pin is connected with a first data receiving circuit, and the second receiving data sending pin is connected with a second data receiving circuit; T. The circuit also comprises a second resistor and a first capacitor. W; when the first HBS chip is mounted, the first data receiving circuit is mounted, and the second data receiving circuit is not mounted; W; when the second HBS chip is mounted, the second data receiving circuit is mounted, and the first data receiving circuit is not mounted; T. Through selective mounting of components, two types of HBS chips share a peripheral setting circuit, and the circuit does not need to be adjusted and redesigned according to chip adaptation, so that t</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyjEOgkAQBdBtLIx6h_EAJhKUxFIJhspGejIOX5lknd2wK-e38QBWr3lL13QjSG2GZQ1GgybxISERG7WXO8mokQbOTBMEOqu9SMI7ctaHB4lO8tG8dosn-4TNz5XbXpuubneIoUeKLDDkvr4V-1NVHMrqeC7_OV-4jTLP</recordid><startdate>20190412</startdate><enddate>20190412</enddate><creator>XU PENGYANG</creator><creator>WANG QIUCHEN</creator><creator>ZHAO HUAIJIE</creator><creator>SHI JINGFENG</creator><scope>EVB</scope></search><sort><creationdate>20190412</creationdate><title>The invention discloses an HBS chip data receiving compatible circuit</title><author>XU PENGYANG ; WANG QIUCHEN ; ZHAO HUAIJIE ; SHI JINGFENG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN109614365A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2019</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>XU PENGYANG</creatorcontrib><creatorcontrib>WANG QIUCHEN</creatorcontrib><creatorcontrib>ZHAO HUAIJIE</creatorcontrib><creatorcontrib>SHI JINGFENG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>XU PENGYANG</au><au>WANG QIUCHEN</au><au>ZHAO HUAIJIE</au><au>SHI JINGFENG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>The invention discloses an HBS chip data receiving compatible circuit</title><date>2019-04-12</date><risdate>2019</risdate><abstract>The invention discloses an HBS chip data receiving compatible circuit which comprises an HBS chip, and the HBS chip is a first HBS chip or a second HBS chip which packages the same HBS chip. The HBS chip comprises a first receiving data sending pin and a second receiving data sending pin; T. The first receiving data sending pin is connected with a first data receiving circuit, and the second receiving data sending pin is connected with a second data receiving circuit; T. The circuit also comprises a second resistor and a first capacitor. W; when the first HBS chip is mounted, the first data receiving circuit is mounted, and the second data receiving circuit is not mounted; W; when the second HBS chip is mounted, the second data receiving circuit is mounted, and the first data receiving circuit is not mounted; T. Through selective mounting of components, two types of HBS chips share a peripheral setting circuit, and the circuit does not need to be adjusted and redesigned according to chip adaptation, so that t</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language chi ; eng
recordid cdi_epo_espacenet_CN109614365A
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title The invention discloses an HBS chip data receiving compatible circuit
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-10T13%3A21%3A11IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=XU%20PENGYANG&rft.date=2019-04-12&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN109614365A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true