Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system

Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system is disclosed. In some aspects, a compressed memory controller (CMC) provides an LLC comprising multiple LLC lines, each providing a plurality of sub-lines the same size as a system cache line. The contents of the system cache line(s) stored within a single LLC line arecompressed and stored in system memory within the memory sub-line region corresponding to the LLC line. A master table stores information indicating how the compressed data for an LLC line is storedin system memory by storing an offset value and a length value for each sub-line within each LLC line. By compressing multiple system cache lines together and storing compressed data in a space normally allocated to multiple uncompressed system lines, the CMC enables compression sizes to be smaller than the memory read/write granularity of the system memory. 本发明揭示在基于中央处理单元CPU的系统中使用多个末级高速缓冲存储器LLC线提供存储器带宽压缩。在些方面中，种经压缩存储器控制器C