Adaptive peripheral component interconnect express link substate initiation for optimal performance and power savings

Systems, methods, and apparatus for adaptively modifying latency times governing entry of a PCIe interface into low power states are described. A method performed by a controller of a PCIe interface includes determining that a burst of data is being transmitted on a PCIe link, configuring a timer to signal when an entry latency period has elapsed after determining that a PCIe link has entered an idle state, causing one or more circuits of the PCIe interface to enter a low-power state when the timer signals that the entry latency period has elapsed before the PCIe link becomes active, and increasing the entry latency period when a number of entries of the PCIe interface to the low-power state that occurs during transmission of the burst of data exceeds a threshold maximum number. 描述了用于自适应地修改管控PCIe接口进入到低功率状态中的等待时间的系统、方法和装置。种由PCIe接口的控制器执行的方法，包括：确定数据突发正在PCIe链路上被传送，将定时器配置成当在确定PCIe链路已进入空闲状态之后流逝了进入等待时间时段时发信令通知，当在该PCIe链路变为活跃之前该定时器发信令通知流逝了该进入等待时间时段时使该PCIe接口的个或多个电路进入低功率状态，以及当在该数据突发的传输期间发生的该PCIe接口进入该低功率状态的次数超过阈值最大次数时增大该