SYSTEM WITH SECURE SOC CONNECTIONS AMONG IP AND MULTIPLE GPIOS, AND CORRESPONDING METHOD

A system with secure SOC connections among IP and multiple GPIOs, and a corresponding method. For example, an integrated circuit includes: one or more intellectual property (IP) cores, one or more general purpose input/output (GPIO) interfaces, and every GPIO interface has the one or more ports, and...

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Hauptverfasser: A L DYNECHE, M TANGTINI, GAETANSTEFANO, S ABENDA
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Sprache:chi ; eng
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creator A L DYNECHE
M TANGTINI
GAETANSTEFANO
S ABENDA
description A system with secure SOC connections among IP and multiple GPIOs, and a corresponding method. For example, an integrated circuit includes: one or more intellectual property (IP) cores, one or more general purpose input/output (GPIO) interfaces, and every GPIO interface has the one or more ports, and one or more safety circuits, with each safety circuit being coupled between the IP core and the GPIO interface. The safety circuit, based on an instruction of the safe state of the IP core, an instruction of the safe state of the GPIO interface, or optionally the instruction of the safe state of the IP core and the instruction of the safe state of the GPIO interface, selectively enables communication between the IP core coupled to the safety circuit and the GPIO interface in the operation. 本公开涉及在IP与多个GPIO之间具有安全SOC连接的系统及对应方法。例如,种集成电路包括:个或多个知识产权(IP)核;个或多个通用输入/输出(GPIO)接口,每个GPIO接口均具有个或多个端口;以及个或多个安全电路,每个安全电路均耦合在IP核与GPIO接口之间。安全电路在操作中基于IP核的安全状态的指示、GPIO接口的安全状态的指示或者IP核的安全状态的指示与GPIO接口的安全状态的指示两者选择性地启用耦合至安全电路的IP核与GPIO接口之间的通信。
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN108572938A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN108572938A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN108572938A3</originalsourceid><addsrcrecordid>eNqNysEKgkAQgGEvHaJ6h-leUEloRxknXXBnlp2V6iQS2ylKsPeniB6g0w8_3zQ560UDWTiZUIMStp5ABQGFmTAYYYXCCldgHBRcgm2bYFxDUDkjuvo-FO9JnXBpPtBSqKWcJ5Nbfx_j4tdZsjxSwHodh2cXx6G_xkd8dcjbTb7Pdoc0L9J_zBv2cTFO</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SYSTEM WITH SECURE SOC CONNECTIONS AMONG IP AND MULTIPLE GPIOS, AND CORRESPONDING METHOD</title><source>esp@cenet</source><creator>A L DYNECHE ; M TANGTINI ; GAETANSTEFANO ; S ABENDA</creator><creatorcontrib>A L DYNECHE ; M TANGTINI ; GAETANSTEFANO ; S ABENDA</creatorcontrib><description>A system with secure SOC connections among IP and multiple GPIOs, and a corresponding method. For example, an integrated circuit includes: one or more intellectual property (IP) cores, one or more general purpose input/output (GPIO) interfaces, and every GPIO interface has the one or more ports, and one or more safety circuits, with each safety circuit being coupled between the IP core and the GPIO interface. The safety circuit, based on an instruction of the safe state of the IP core, an instruction of the safe state of the GPIO interface, or optionally the instruction of the safe state of the IP core and the instruction of the safe state of the GPIO interface, selectively enables communication between the IP core coupled to the safety circuit and the GPIO interface in the operation. 本公开涉及在IP与多个GPIO之间具有安全SOC连接的系统及对应方法。例如,种集成电路包括:个或多个知识产权(IP)核;个或多个通用输入/输出(GPIO)接口,每个GPIO接口均具有个或多个端口;以及个或多个安全电路,每个安全电路均耦合在IP核与GPIO接口之间。安全电路在操作中基于IP核的安全状态的指示、GPIO接口的安全状态的指示或者IP核的安全状态的指示与GPIO接口的安全状态的指示两者选择性地启用耦合至安全电路的IP核与GPIO接口之间的通信。</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20180925&amp;DB=EPODOC&amp;CC=CN&amp;NR=108572938A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20180925&amp;DB=EPODOC&amp;CC=CN&amp;NR=108572938A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>A L DYNECHE</creatorcontrib><creatorcontrib>M TANGTINI</creatorcontrib><creatorcontrib>GAETANSTEFANO</creatorcontrib><creatorcontrib>S ABENDA</creatorcontrib><title>SYSTEM WITH SECURE SOC CONNECTIONS AMONG IP AND MULTIPLE GPIOS, AND CORRESPONDING METHOD</title><description>A system with secure SOC connections among IP and multiple GPIOs, and a corresponding method. For example, an integrated circuit includes: one or more intellectual property (IP) cores, one or more general purpose input/output (GPIO) interfaces, and every GPIO interface has the one or more ports, and one or more safety circuits, with each safety circuit being coupled between the IP core and the GPIO interface. The safety circuit, based on an instruction of the safe state of the IP core, an instruction of the safe state of the GPIO interface, or optionally the instruction of the safe state of the IP core and the instruction of the safe state of the GPIO interface, selectively enables communication between the IP core coupled to the safety circuit and the GPIO interface in the operation. 本公开涉及在IP与多个GPIO之间具有安全SOC连接的系统及对应方法。例如,种集成电路包括:个或多个知识产权(IP)核;个或多个通用输入/输出(GPIO)接口,每个GPIO接口均具有个或多个端口;以及个或多个安全电路,每个安全电路均耦合在IP核与GPIO接口之间。安全电路在操作中基于IP核的安全状态的指示、GPIO接口的安全状态的指示或者IP核的安全状态的指示与GPIO接口的安全状态的指示两者选择性地启用耦合至安全电路的IP核与GPIO接口之间的通信。</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNysEKgkAQgGEvHaJ6h-leUEloRxknXXBnlp2V6iQS2ylKsPeniB6g0w8_3zQ560UDWTiZUIMStp5ABQGFmTAYYYXCCldgHBRcgm2bYFxDUDkjuvo-FO9JnXBpPtBSqKWcJ5Nbfx_j4tdZsjxSwHodh2cXx6G_xkd8dcjbTb7Pdoc0L9J_zBv2cTFO</recordid><startdate>20180925</startdate><enddate>20180925</enddate><creator>A L DYNECHE</creator><creator>M TANGTINI</creator><creator>GAETANSTEFANO</creator><creator>S ABENDA</creator><scope>EVB</scope></search><sort><creationdate>20180925</creationdate><title>SYSTEM WITH SECURE SOC CONNECTIONS AMONG IP AND MULTIPLE GPIOS, AND CORRESPONDING METHOD</title><author>A L DYNECHE ; M TANGTINI ; GAETANSTEFANO ; S ABENDA</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN108572938A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2018</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>A L DYNECHE</creatorcontrib><creatorcontrib>M TANGTINI</creatorcontrib><creatorcontrib>GAETANSTEFANO</creatorcontrib><creatorcontrib>S ABENDA</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>A L DYNECHE</au><au>M TANGTINI</au><au>GAETANSTEFANO</au><au>S ABENDA</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SYSTEM WITH SECURE SOC CONNECTIONS AMONG IP AND MULTIPLE GPIOS, AND CORRESPONDING METHOD</title><date>2018-09-25</date><risdate>2018</risdate><abstract>A system with secure SOC connections among IP and multiple GPIOs, and a corresponding method. For example, an integrated circuit includes: one or more intellectual property (IP) cores, one or more general purpose input/output (GPIO) interfaces, and every GPIO interface has the one or more ports, and one or more safety circuits, with each safety circuit being coupled between the IP core and the GPIO interface. The safety circuit, based on an instruction of the safe state of the IP core, an instruction of the safe state of the GPIO interface, or optionally the instruction of the safe state of the IP core and the instruction of the safe state of the GPIO interface, selectively enables communication between the IP core coupled to the safety circuit and the GPIO interface in the operation. 本公开涉及在IP与多个GPIO之间具有安全SOC连接的系统及对应方法。例如,种集成电路包括:个或多个知识产权(IP)核;个或多个通用输入/输出(GPIO)接口,每个GPIO接口均具有个或多个端口;以及个或多个安全电路,每个安全电路均耦合在IP核与GPIO接口之间。安全电路在操作中基于IP核的安全状态的指示、GPIO接口的安全状态的指示或者IP核的安全状态的指示与GPIO接口的安全状态的指示两者选择性地启用耦合至安全电路的IP核与GPIO接口之间的通信。</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title SYSTEM WITH SECURE SOC CONNECTIONS AMONG IP AND MULTIPLE GPIOS, AND CORRESPONDING METHOD
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