Fiducial mark for chip bonding
A flexible multilayer construction (100) for mounting a light emitting semiconductor device (200) (LESD), includes a flexible dielectric substrate (110) having an LESD mounting region (120), first andsecond electrically conductive pads (130, 140) disposed in the LESD mounting region for electrically...
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| creator | KOSUGI HIROMITSU FOO SIANG SIN PALANISWAMY RAVI NARAG ALEJANDRO ALDRIN II A |
| description | A flexible multilayer construction (100) for mounting a light emitting semiconductor device (200) (LESD), includes a flexible dielectric substrate (110) having an LESD mounting region (120), first andsecond electrically conductive pads (130, 140) disposed in the LESD mounting region for electrically connecting to corresponding first and second electrically conductive terminals of an LESD (200) received in the LESD mounting region, and a first fiducial alignment mark (150) for an accurate placement of an LESD in the LESD mounting region. The first fiducial alignment mark is disposed within theLESD mounting region.
本发明公开了种用于安装发光半导体器件(200)(LESD)的柔性多层构造(100)，该柔性多层构造包括具有LESD安装区域(120)的柔性介电基板(110)，设置在LESD安装区域中用于电连接到在LESD安装区域中接收的LESD(200)的对应的第导电端子和第二导电端子的第导电垫(130)和第二导电垫(140)，以及用于LESD在LESD安装区域中的精确放置的第基准对准标记(150)。第基准对准标记设置在LESD安装区域内。 |
| format | Patent |
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本发明公开了种用于安装发光半导体器件(200)(LESD)的柔性多层构造(100)，该柔性多层构造包括具有LESD安装区域(120)的柔性介电基板(110)，设置在LESD安装区域中用于电连接到在LESD安装区域中接收的LESD(200)的对应的第导电端子和第二导电端子的第导电垫(130)和第二导电垫(140)，以及用于LESD在LESD安装区域中的精确放置的第基准对准标记(150)。第基准对准标记设置在LESD安装区域内。</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180417&DB=EPODOC&CC=CN&NR=107926113A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180417&DB=EPODOC&CC=CN&NR=107926113A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KOSUGI HIROMITSU</creatorcontrib><creatorcontrib>FOO SIANG SIN</creatorcontrib><creatorcontrib>PALANISWAMY RAVI</creatorcontrib><creatorcontrib>NARAG ALEJANDRO ALDRIN II A</creatorcontrib><title>Fiducial mark for chip bonding</title><description>A flexible multilayer construction (100) for mounting a light emitting semiconductor device (200) (LESD), includes a flexible dielectric substrate (110) having an LESD mounting region (120), first andsecond electrically conductive pads (130, 140) disposed in the LESD mounting region for electrically connecting to corresponding first and second electrically conductive terminals of an LESD (200) received in the LESD mounting region, and a first fiducial alignment mark (150) for an accurate placement of an LESD in the LESD mounting region. The first fiducial alignment mark is disposed within theLESD mounting region.
本发明公开了种用于安装发光半导体器件(200)(LESD)的柔性多层构造(100)，该柔性多层构造包括具有LESD安装区域(120)的柔性介电基板(110)，设置在LESD安装区域中用于电连接到在LESD安装区域中接收的LESD(200)的对应的第导电端子和第二导电端子的第导电垫(130)和第二导电垫(140)，以及用于LESD在LESD安装区域中的精确放置的第基准对准标记(150)。第基准对准标记设置在LESD安装区域内。</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJBzy0wpTc5MzFHITSzKVkjLL1JIzsgsUEjKz0vJzEvnYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxzn6GBuaWRmaGhsaOxsSoAQDQOSQZ</recordid><startdate>20180417</startdate><enddate>20180417</enddate><creator>KOSUGI HIROMITSU</creator><creator>FOO SIANG SIN</creator><creator>PALANISWAMY RAVI</creator><creator>NARAG ALEJANDRO ALDRIN II A</creator><scope>EVB</scope></search><sort><creationdate>20180417</creationdate><title>Fiducial mark for chip bonding</title><author>KOSUGI HIROMITSU ; FOO SIANG SIN ; PALANISWAMY RAVI ; NARAG ALEJANDRO ALDRIN II A</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN107926113A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2018</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KOSUGI HIROMITSU</creatorcontrib><creatorcontrib>FOO SIANG SIN</creatorcontrib><creatorcontrib>PALANISWAMY RAVI</creatorcontrib><creatorcontrib>NARAG ALEJANDRO ALDRIN II A</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KOSUGI HIROMITSU</au><au>FOO SIANG SIN</au><au>PALANISWAMY RAVI</au><au>NARAG ALEJANDRO ALDRIN II A</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Fiducial mark for chip bonding</title><date>2018-04-17</date><risdate>2018</risdate><abstract>A flexible multilayer construction (100) for mounting a light emitting semiconductor device (200) (LESD), includes a flexible dielectric substrate (110) having an LESD mounting region (120), first andsecond electrically conductive pads (130, 140) disposed in the LESD mounting region for electrically connecting to corresponding first and second electrically conductive terminals of an LESD (200) received in the LESD mounting region, and a first fiducial alignment mark (150) for an accurate placement of an LESD in the LESD mounting region. The first fiducial alignment mark is disposed within theLESD mounting region.
本发明公开了种用于安装发光半导体器件(200)(LESD)的柔性多层构造(100)，该柔性多层构造包括具有LESD安装区域(120)的柔性介电基板(110)，设置在LESD安装区域中用于电连接到在LESD安装区域中接收的LESD(200)的对应的第导电端子和第二导电端子的第导电垫(130)和第二导电垫(140)，以及用于LESD在LESD安装区域中的精确放置的第基准对准标记(150)。第基准对准标记设置在LESD安装区域内。</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS SEMICONDUCTOR DEVICES |
| title | Fiducial mark for chip bonding |
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