TRANSISTOR HAVING HIGH ELECTRON MOBILITY
The invention relates to a method for producing a transistor (100, 200, 300, 400, 500, 600, 700) having high electron mobility, comprising a substrate (101, 201, 301, 401, 501, 601, 701) having a heterostructure (103, 203, 303, 403, 503, 603, 703), in particular an AlGaN/GaN heterostructure, compris...
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creator | JAUSS SIMON ALEXANDER GRIEB MICHAEL SCHWAIGER STEPHAN |
description | The invention relates to a method for producing a transistor (100, 200, 300, 400, 500, 600, 700) having high electron mobility, comprising a substrate (101, 201, 301, 401, 501, 601, 701) having a heterostructure (103, 203, 303, 403, 503, 603, 703), in particular an AlGaN/GaN heterostructure, comprising the steps: producing (8030) a gate electrode by structuring a semiconductor layer, which is applied to the heterostructure (103, 203, 303, 403, 503, 603, 703), wherein the semiconductor layer (104, 204, 304, 404, 504, 604, 704) in particular comprises polysilicon, applying (8040) a passivation layer (105, 205, 305, 405, 505, 605) to the semiconductor layer (104, 204, 304, 404, 504, 604, 704), forming (8070) drain regions and source regions, in that first vertical openings are produced, whichreach at least into the heterostructure (103, 203, 303, 403, 503, 603, 703), producing (8080) ohmic contacts in the drain regions and in the source regions by partial filling of the first vertical openings with a first metal |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN107810559A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN107810559A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN107810559A3</originalsourceid><addsrcrecordid>eNrjZNAICXL0C_YMDvEPUvBwDPP0c1fw8HT3UHD1cXUOCfL3U_D1d_L08QyJ5GFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8c5-hgbmFoYGpqaWjsbEqAEAIKokUg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>TRANSISTOR HAVING HIGH ELECTRON MOBILITY</title><source>esp@cenet</source><creator>JAUSS SIMON ALEXANDER ; GRIEB MICHAEL ; SCHWAIGER STEPHAN</creator><creatorcontrib>JAUSS SIMON ALEXANDER ; GRIEB MICHAEL ; SCHWAIGER STEPHAN</creatorcontrib><description>The invention relates to a method for producing a transistor (100, 200, 300, 400, 500, 600, 700) having high electron mobility, comprising a substrate (101, 201, 301, 401, 501, 601, 701) having a heterostructure (103, 203, 303, 403, 503, 603, 703), in particular an AlGaN/GaN heterostructure, comprising the steps: producing (8030) a gate electrode by structuring a semiconductor layer, which is applied to the heterostructure (103, 203, 303, 403, 503, 603, 703), wherein the semiconductor layer (104, 204, 304, 404, 504, 604, 704) in particular comprises polysilicon, applying (8040) a passivation layer (105, 205, 305, 405, 505, 605) to the semiconductor layer (104, 204, 304, 404, 504, 604, 704), forming (8070) drain regions and source regions, in that first vertical openings are produced, whichreach at least into the heterostructure (103, 203, 303, 403, 503, 603, 703), producing (8080) ohmic contacts in the drain regions and in the source regions by partial filling of the first vertical openings with a first metal</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180316&DB=EPODOC&CC=CN&NR=107810559A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180316&DB=EPODOC&CC=CN&NR=107810559A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JAUSS SIMON ALEXANDER</creatorcontrib><creatorcontrib>GRIEB MICHAEL</creatorcontrib><creatorcontrib>SCHWAIGER STEPHAN</creatorcontrib><title>TRANSISTOR HAVING HIGH ELECTRON MOBILITY</title><description>The invention relates to a method for producing a transistor (100, 200, 300, 400, 500, 600, 700) having high electron mobility, comprising a substrate (101, 201, 301, 401, 501, 601, 701) having a heterostructure (103, 203, 303, 403, 503, 603, 703), in particular an AlGaN/GaN heterostructure, comprising the steps: producing (8030) a gate electrode by structuring a semiconductor layer, which is applied to the heterostructure (103, 203, 303, 403, 503, 603, 703), wherein the semiconductor layer (104, 204, 304, 404, 504, 604, 704) in particular comprises polysilicon, applying (8040) a passivation layer (105, 205, 305, 405, 505, 605) to the semiconductor layer (104, 204, 304, 404, 504, 604, 704), forming (8070) drain regions and source regions, in that first vertical openings are produced, whichreach at least into the heterostructure (103, 203, 303, 403, 503, 603, 703), producing (8080) ohmic contacts in the drain regions and in the source regions by partial filling of the first vertical openings with a first metal</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAICXL0C_YMDvEPUvBwDPP0c1fw8HT3UHD1cXUOCfL3U_D1d_L08QyJ5GFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8c5-hgbmFoYGpqaWjsbEqAEAIKokUg</recordid><startdate>20180316</startdate><enddate>20180316</enddate><creator>JAUSS SIMON ALEXANDER</creator><creator>GRIEB MICHAEL</creator><creator>SCHWAIGER STEPHAN</creator><scope>EVB</scope></search><sort><creationdate>20180316</creationdate><title>TRANSISTOR HAVING HIGH ELECTRON MOBILITY</title><author>JAUSS SIMON ALEXANDER ; GRIEB MICHAEL ; SCHWAIGER STEPHAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN107810559A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2018</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>JAUSS SIMON ALEXANDER</creatorcontrib><creatorcontrib>GRIEB MICHAEL</creatorcontrib><creatorcontrib>SCHWAIGER STEPHAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JAUSS SIMON ALEXANDER</au><au>GRIEB MICHAEL</au><au>SCHWAIGER STEPHAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>TRANSISTOR HAVING HIGH ELECTRON MOBILITY</title><date>2018-03-16</date><risdate>2018</risdate><abstract>The invention relates to a method for producing a transistor (100, 200, 300, 400, 500, 600, 700) having high electron mobility, comprising a substrate (101, 201, 301, 401, 501, 601, 701) having a heterostructure (103, 203, 303, 403, 503, 603, 703), in particular an AlGaN/GaN heterostructure, comprising the steps: producing (8030) a gate electrode by structuring a semiconductor layer, which is applied to the heterostructure (103, 203, 303, 403, 503, 603, 703), wherein the semiconductor layer (104, 204, 304, 404, 504, 604, 704) in particular comprises polysilicon, applying (8040) a passivation layer (105, 205, 305, 405, 505, 605) to the semiconductor layer (104, 204, 304, 404, 504, 604, 704), forming (8070) drain regions and source regions, in that first vertical openings are produced, whichreach at least into the heterostructure (103, 203, 303, 403, 503, 603, 703), producing (8080) ohmic contacts in the drain regions and in the source regions by partial filling of the first vertical openings with a first metal</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | TRANSISTOR HAVING HIGH ELECTRON MOBILITY |
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