I2C (Inter-Integrated Circuit) host adapter system
The invention provides an I2C (Inter-Integrated Circuit) host adapter system. The I2C host adapter system comprises a to-be-tested server, an I2C master control device and an electronic apparatus; theto-be-tested server is provided with at least one I2C chip; the I2C master control device is electri...
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| creator | YAN QIYUAN |
| description | The invention provides an I2C (Inter-Integrated Circuit) host adapter system. The I2C host adapter system comprises a to-be-tested server, an I2C master control device and an electronic apparatus; theto-be-tested server is provided with at least one I2C chip; the I2C master control device is electrically connected with the I2C chip of the to-be-tested server, and provides a webpage testing interface corresponding to the I2C chip; the electronic apparatus is connected to the I2C master control device via a network; a user controls the I2C master control device via the electronic apparatus andthrough the webpage testing interface to send a testing instruction, such that after the I2C master control device receives the testing instruction, the testing instruction is transmitted to a designated I2C chip on the to-be-tested server and a testing result generated after the designated I2C chip executes the testing instruction is transmitted back to the electronic apparatus via the network.
本发明提供种I2C主机适配器系统，其包括：待测服务器、 |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN107590034A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN107590034A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN107590034A3</originalsourceid><addsrcrecordid>eNrjZDDyNHJW0PDMK0kt0gWR6UWJJakpCs6ZRcmlmSWaChn5xSUKiSmJBUAFCsWVxSWpuTwMrGmJOcWpvFCam0HRzTXE2UM3tSA_PrW4IDE5NS-1JN7Zz9DA3NTSwMDYxNGYGDUARPUrDw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>I2C (Inter-Integrated Circuit) host adapter system</title><source>esp@cenet</source><creator>YAN QIYUAN</creator><creatorcontrib>YAN QIYUAN</creatorcontrib><description>The invention provides an I2C (Inter-Integrated Circuit) host adapter system. The I2C host adapter system comprises a to-be-tested server, an I2C master control device and an electronic apparatus; theto-be-tested server is provided with at least one I2C chip; the I2C master control device is electrically connected with the I2C chip of the to-be-tested server, and provides a webpage testing interface corresponding to the I2C chip; the electronic apparatus is connected to the I2C master control device via a network; a user controls the I2C master control device via the electronic apparatus andthrough the webpage testing interface to send a testing instruction, such that after the I2C master control device receives the testing instruction, the testing instruction is transmitted to a designated I2C chip on the to-be-tested server and a testing result generated after the designated I2C chip executes the testing instruction is transmitted back to the electronic apparatus via the network.
本发明提供种I2C主机适配器系统，其包括：待测服务器、</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180116&DB=EPODOC&CC=CN&NR=107590034A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25544,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180116&DB=EPODOC&CC=CN&NR=107590034A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YAN QIYUAN</creatorcontrib><title>I2C (Inter-Integrated Circuit) host adapter system</title><description>The invention provides an I2C (Inter-Integrated Circuit) host adapter system. The I2C host adapter system comprises a to-be-tested server, an I2C master control device and an electronic apparatus; theto-be-tested server is provided with at least one I2C chip; the I2C master control device is electrically connected with the I2C chip of the to-be-tested server, and provides a webpage testing interface corresponding to the I2C chip; the electronic apparatus is connected to the I2C master control device via a network; a user controls the I2C master control device via the electronic apparatus andthrough the webpage testing interface to send a testing instruction, such that after the I2C master control device receives the testing instruction, the testing instruction is transmitted to a designated I2C chip on the to-be-tested server and a testing result generated after the designated I2C chip executes the testing instruction is transmitted back to the electronic apparatus via the network.
本发明提供种I2C主机适配器系统，其包括：待测服务器、</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDDyNHJW0PDMK0kt0gWR6UWJJakpCs6ZRcmlmSWaChn5xSUKiSmJBUAFCsWVxSWpuTwMrGmJOcWpvFCam0HRzTXE2UM3tSA_PrW4IDE5NS-1JN7Zz9DA3NTSwMDYxNGYGDUARPUrDw</recordid><startdate>20180116</startdate><enddate>20180116</enddate><creator>YAN QIYUAN</creator><scope>EVB</scope></search><sort><creationdate>20180116</creationdate><title>I2C (Inter-Integrated Circuit) host adapter system</title><author>YAN QIYUAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN107590034A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2018</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>YAN QIYUAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YAN QIYUAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>I2C (Inter-Integrated Circuit) host adapter system</title><date>2018-01-16</date><risdate>2018</risdate><abstract>The invention provides an I2C (Inter-Integrated Circuit) host adapter system. The I2C host adapter system comprises a to-be-tested server, an I2C master control device and an electronic apparatus; theto-be-tested server is provided with at least one I2C chip; the I2C master control device is electrically connected with the I2C chip of the to-be-tested server, and provides a webpage testing interface corresponding to the I2C chip; the electronic apparatus is connected to the I2C master control device via a network; a user controls the I2C master control device via the electronic apparatus andthrough the webpage testing interface to send a testing instruction, such that after the I2C master control device receives the testing instruction, the testing instruction is transmitted to a designated I2C chip on the to-be-tested server and a testing result generated after the designated I2C chip executes the testing instruction is transmitted back to the electronic apparatus via the network.
本发明提供种I2C主机适配器系统，其包括：待测服务器、</abstract><oa>free_for_read</oa></addata></record> |
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| language | chi ; eng |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | I2C (Inter-Integrated Circuit) host adapter system |
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