Control method and device for high-speed-access double-data-rate synchronous dynamic random memory
The invention discloses a control method and device for high-speed-access double-data-rate synchronous dynamic random memory. The method is characterized by comprising the following steps: dividing the double-data-rate synchronous dynamic random memory (DDR) into variable caching blocks according to...
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| creator | YUE LEITING |
| description | The invention discloses a control method and device for high-speed-access double-data-rate synchronous dynamic random memory. The method is characterized by comprising the following steps: dividing the double-data-rate synchronous dynamic random memory (DDR) into variable caching blocks according to a dynamic configuration strategy; and when carrying out reading and writing operation based on the variable caching blocks, dispatching reading/writing operation of a plurality of channels according to a weighted round robin strategy, and balancing reading/writing band width.
本发明公开了种高速访问双倍速率同步动态随机存储器的控制方法及装置，其特征在于，所述方法包括：将双倍速率同步动态随机存储器(DDR)按照动态配置策略划分为可变的缓存块；基于所述可变的缓存块进行读写操作时，根据加权循环调度策略对针对多个通道的读/写操作进行调度，并对读/写带宽进行平衡。 |
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本发明公开了种高速访问双倍速率同步动态随机存储器的控制方法及装置，其特征在于，所述方法包括：将双倍速率同步动态随机存储器(DDR)按照动态配置策略划分为可变的缓存块；基于所述可变的缓存块进行读写操作时，根据加权循环调度策略对针对多个通道的读/写操作进行调度，并对读/写带宽进行平衡。</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170926&DB=EPODOC&CC=CN&NR=107204198A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170926&DB=EPODOC&CC=CN&NR=107204198A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YUE LEITING</creatorcontrib><title>Control method and device for high-speed-access double-data-rate synchronous dynamic random memory</title><description>The invention discloses a control method and device for high-speed-access double-data-rate synchronous dynamic random memory. The method is characterized by comprising the following steps: dividing the double-data-rate synchronous dynamic random memory (DDR) into variable caching blocks according to a dynamic configuration strategy; and when carrying out reading and writing operation based on the variable caching blocks, dispatching reading/writing operation of a plurality of channels according to a weighted round robin strategy, and balancing reading/writing band width.
本发明公开了种高速访问双倍速率同步动态随机存储器的控制方法及装置，其特征在于，所述方法包括：将双倍速率同步动态随机存储器(DDR)按照动态配置策略划分为可变的缓存块；基于所述可变的缓存块进行读写操作时，根据加权循环调度策略对针对多个通道的读/写操作进行调度，并对读/写带宽进行平衡。</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjLEKwjAURbs4iPoPzw8ItCqooxTFycm9vCa3TSHJK0kq9O_t4Ac4neEczrpoawk5iiOPbMUQB0MGn0GDOolkh96qNAJGsdZIiYxMrYMynFlFzqA0B22jBJkWOQf2g6a4bMQvTy9x3harjl3C7sdNsX_c3_VTYZQGaWSNgNzUr6o8H8pTdb3cjv80X1BFPjc</recordid><startdate>20170926</startdate><enddate>20170926</enddate><creator>YUE LEITING</creator><scope>EVB</scope></search><sort><creationdate>20170926</creationdate><title>Control method and device for high-speed-access double-data-rate synchronous dynamic random memory</title><author>YUE LEITING</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN107204198A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2017</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>YUE LEITING</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YUE LEITING</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Control method and device for high-speed-access double-data-rate synchronous dynamic random memory</title><date>2017-09-26</date><risdate>2017</risdate><abstract>The invention discloses a control method and device for high-speed-access double-data-rate synchronous dynamic random memory. The method is characterized by comprising the following steps: dividing the double-data-rate synchronous dynamic random memory (DDR) into variable caching blocks according to a dynamic configuration strategy; and when carrying out reading and writing operation based on the variable caching blocks, dispatching reading/writing operation of a plurality of channels according to a weighted round robin strategy, and balancing reading/writing band width.
本发明公开了种高速访问双倍速率同步动态随机存储器的控制方法及装置，其特征在于，所述方法包括：将双倍速率同步动态随机存储器(DDR)按照动态配置策略划分为可变的缓存块；基于所述可变的缓存块进行读写操作时，根据加权循环调度策略对针对多个通道的读/写操作进行调度，并对读/写带宽进行平衡。</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES |
| title | Control method and device for high-speed-access double-data-rate synchronous dynamic random memory |
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