Programmable delay circuit block

A programmable delay circuit block (100) includes an input stage (102) having a cascade input (112) and a clock input (114), wherein the input stage (102) passes a signal received at the cascade input (112) or a signal received at the clock input (114). The programmable delay circuit block (100) fur...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	GANUSOV ILYA K, DEVLIN BENJAMIN S
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE
Online-Zugang:	Volltext bestellen
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