Latch comparator circuits and methods

The present disclosure includes circuits and methods for latching signals. In one embodiment, two inverters (204, 205 and 206, 207) are configured back to back to latch a signal. Each inverter includes a capacitor (C1, C2) configured between control terminals of inverter transistors. In one embodiment, the circuit is part of a comparator. First and second voltages (Vip, Vin) are received on control terminals of differential transistors (201, 202), and a differential output signal (Out1, Out2) is coupled to two back to back inverters. In one embodiment, a circuit is disabled (latch signal at 0) and a voltage on a control terminal of a transistor (204, 206) in an inverter is set below a reference (Vref), such as a power supply (Vs), to increase the speed of the circuit. 本公开包括用于对信号进行锁存的电路和方法。在个实施例中，两个逆变器(204、205与206、207)被配置为对信号进行背靠背锁存。每个逆变器包括被配置在逆变器晶体管的控制端子之间的电容器(C1、C2)。在个实施例中，该电路是比较器的部分。第和第二电压(Vip、Vin)在差分晶体管(201、202)的控制端子上被接收，并且差分输出信号(Out1、Out2)被耦合至两个背靠背逆变器。在个实施例中，电路被禁用(锁存信号为0)并且逆变器中的晶体管(204、206)的控制端子上的电压被设置为低于