Multiphase delay locking loop

The invention discloses a multiphase delay locking loop, and the loop comprises a first delay locking circuit, a clock rate edge synthesis circuit, a second delay locking circuit, a duplication delay circuit, and a logic selection circuit. The first delay locking circuit enables an inputted first clock rate signal with a first clock rate period to be divided into N phase delay units. The clock rate edge synthesis circuit enables the signals between the first phase of the first time rate signal in a first time rate period and the second phase of the first time rate signal in a next time rate period to be synthesized into a second time rate signal. The second delay locking circuit enables a second time rate period of the second time rate signal to be divided into N phase delay units. The logic selection circuit selects the time delay amounts of the first delay locking circuit and the duplication delay circuit. The first delay locking circuit carries out the corresponding phase delay of the first time rate signa