Operating system-managed interrupt steering in multiprocessor systems
An operating system is provided in which an interrupt router dynamically steers each interrupt to one or more processors within set of processors based on overall load information from the set of processors. An interrupt source is assigned to a processor based on the load imposed by the interrupt so...
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creator | BARAKAT YOUSSEF FATEMIEH OMID BROWN TRISTAN RAFFMAN ANDREW KIM MIN-SANG WOHLGEMUTH JASON |
description | An operating system is provided in which an interrupt router dynamically steers each interrupt to one or more processors within set of processors based on overall load information from the set of processors. An interrupt source is assigned to a processor based on the load imposed by the interrupt source and the target overall load for the processor. For example, each processor can maintain information about each interrupt it processes over time. The operating system receives this historical load information to determine an expected load for interrupts of a given type from a given device, an overall load on the system, and a target load for each processor. Given a set of interrupt sources, their expected loads, and target load for each processor, each interrupt source can be assigned dynamically to a processor during runtime of the system. On a regular basis, these assignments can be changed given current operating conditions of the system. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN105378668A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN105378668A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN105378668A3</originalsourceid><addsrcrecordid>eNrjZHD1L0gtSizJzEtXKK4sLknN1c1NzEtMT01RyMwrSS0qKi0oUQAKpxaBVGTmKeSW5pRkFhTlJ6cWF-cXQfUU8zCwpiXmFKfyQmluBkU31xBnD93Ugvz41OKCxOTUvNSSeGc_QwNTY3MLMzMLR2Ni1AAAi2Q0lA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Operating system-managed interrupt steering in multiprocessor systems</title><source>esp@cenet</source><creator>BARAKAT YOUSSEF ; FATEMIEH OMID ; BROWN TRISTAN ; RAFFMAN ANDREW ; KIM MIN-SANG ; WOHLGEMUTH JASON</creator><creatorcontrib>BARAKAT YOUSSEF ; FATEMIEH OMID ; BROWN TRISTAN ; RAFFMAN ANDREW ; KIM MIN-SANG ; WOHLGEMUTH JASON</creatorcontrib><description>An operating system is provided in which an interrupt router dynamically steers each interrupt to one or more processors within set of processors based on overall load information from the set of processors. An interrupt source is assigned to a processor based on the load imposed by the interrupt source and the target overall load for the processor. For example, each processor can maintain information about each interrupt it processes over time. The operating system receives this historical load information to determine an expected load for interrupts of a given type from a given device, an overall load on the system, and a target load for each processor. Given a set of interrupt sources, their expected loads, and target load for each processor, each interrupt source can be assigned dynamically to a processor during runtime of the system. On a regular basis, these assignments can be changed given current operating conditions of the system.</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160302&DB=EPODOC&CC=CN&NR=105378668A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160302&DB=EPODOC&CC=CN&NR=105378668A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BARAKAT YOUSSEF</creatorcontrib><creatorcontrib>FATEMIEH OMID</creatorcontrib><creatorcontrib>BROWN TRISTAN</creatorcontrib><creatorcontrib>RAFFMAN ANDREW</creatorcontrib><creatorcontrib>KIM MIN-SANG</creatorcontrib><creatorcontrib>WOHLGEMUTH JASON</creatorcontrib><title>Operating system-managed interrupt steering in multiprocessor systems</title><description>An operating system is provided in which an interrupt router dynamically steers each interrupt to one or more processors within set of processors based on overall load information from the set of processors. An interrupt source is assigned to a processor based on the load imposed by the interrupt source and the target overall load for the processor. For example, each processor can maintain information about each interrupt it processes over time. The operating system receives this historical load information to determine an expected load for interrupts of a given type from a given device, an overall load on the system, and a target load for each processor. Given a set of interrupt sources, their expected loads, and target load for each processor, each interrupt source can be assigned dynamically to a processor during runtime of the system. On a regular basis, these assignments can be changed given current operating conditions of the system.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHD1L0gtSizJzEtXKK4sLknN1c1NzEtMT01RyMwrSS0qKi0oUQAKpxaBVGTmKeSW5pRkFhTlJ6cWF-cXQfUU8zCwpiXmFKfyQmluBkU31xBnD93Ugvz41OKCxOTUvNSSeGc_QwNTY3MLMzMLR2Ni1AAAi2Q0lA</recordid><startdate>20160302</startdate><enddate>20160302</enddate><creator>BARAKAT YOUSSEF</creator><creator>FATEMIEH OMID</creator><creator>BROWN TRISTAN</creator><creator>RAFFMAN ANDREW</creator><creator>KIM MIN-SANG</creator><creator>WOHLGEMUTH JASON</creator><scope>EVB</scope></search><sort><creationdate>20160302</creationdate><title>Operating system-managed interrupt steering in multiprocessor systems</title><author>BARAKAT YOUSSEF ; FATEMIEH OMID ; BROWN TRISTAN ; RAFFMAN ANDREW ; KIM MIN-SANG ; WOHLGEMUTH JASON</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN105378668A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2016</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>BARAKAT YOUSSEF</creatorcontrib><creatorcontrib>FATEMIEH OMID</creatorcontrib><creatorcontrib>BROWN TRISTAN</creatorcontrib><creatorcontrib>RAFFMAN ANDREW</creatorcontrib><creatorcontrib>KIM MIN-SANG</creatorcontrib><creatorcontrib>WOHLGEMUTH JASON</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BARAKAT YOUSSEF</au><au>FATEMIEH OMID</au><au>BROWN TRISTAN</au><au>RAFFMAN ANDREW</au><au>KIM MIN-SANG</au><au>WOHLGEMUTH JASON</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Operating system-managed interrupt steering in multiprocessor systems</title><date>2016-03-02</date><risdate>2016</risdate><abstract>An operating system is provided in which an interrupt router dynamically steers each interrupt to one or more processors within set of processors based on overall load information from the set of processors. An interrupt source is assigned to a processor based on the load imposed by the interrupt source and the target overall load for the processor. For example, each processor can maintain information about each interrupt it processes over time. The operating system receives this historical load information to determine an expected load for interrupts of a given type from a given device, an overall load on the system, and a target load for each processor. Given a set of interrupt sources, their expected loads, and target load for each processor, each interrupt source can be assigned dynamically to a processor during runtime of the system. On a regular basis, these assignments can be changed given current operating conditions of the system.</abstract><oa>free_for_read</oa></addata></record> |
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language | chi ; eng |
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subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | Operating system-managed interrupt steering in multiprocessor systems |
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