Chip scale packaging method

The invention discloses a chip scale packaging method. Wafers with scribing grooves are taken as processing objects. The packaging method comprises the steps specifically: step a, preparing conductive lugs; step b, thinning; step c, coating an insulation protecting adhesive layer; step d, cutting, wherein the cutting step is executed by steps of attaching the back surface of the insulation protection adhesive layer of the wafers prepared in the step c to an adhesive film to be fixed, and then cutting along the scribing grooves in the wafers for the first time, and the cutting depth is equal to the sum of the thicknesses of the wafers and the insulation protecting adhesive layer; step e, coating the insulation protecting adhesive layer for the second time; and step f, cutting for the second time, wherein the step of cutting for the second time is performed by steps of detecting the positions of the scribing grooves in the step d in the wafers prepared after the step e by an electromagnetic wave detecting instrument for cutting for the second time, and the width in the secondary-cutting is less than the width of the primary-cutting in the step d; and then peeling each crystalline grain off the adhesive film to prepare packaged devices. The preparation method is reasonable in method, high in production efficiency and low in investment cost.