SRAM (Static Random Access Memory) output latch circuit

The invention provides an SRAM (Static Random Access Memory) output latch circuit, which at least comprises a sense amplifier, a presetting bit signal generation circuit and an RS (Reset Set) latch circuit, wherein the sense amplifier is used for amplifying a signal; the presetting bit signal generation circuit is used for generating a presetting bit signal; the RS latch circuit is connected to the output end of the sense amplifier and the output end of the presetting bit signal generation circuit; the presetting bit signal generation circuit causes an RS latch to output a signal "1" in advance; when the input signal of the sense amplifier is "0", the output signal of the RS latch is jumped to the signal "0" from the signal "1"; and when the input signal of the sense amplifier is "1", the output signal of the RS latch is kept as the signal "1". The SRAM output latch circuit shortens time for outputting "1" through the increase of one presetting bit signal, and a purpose that the integral access time of the SRAM is shortened is achieved so as to improve the performance of the SRAM.