Multi-processor architecture and method
Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interfac...
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| creator | MOREIN STEPHEN SOLKI SHAHIN GROSSMAN MARK S |
| description | Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC Embodiments is usable with known bus protocols. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN105005542A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN105005542A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN105005542A3</originalsourceid><addsrcrecordid>eNrjZFD3Lc0pydQtKMpPTi0uzi9SSCxKzsgsSU0uKS1KVUjMS1HITS3JyE_hYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxzn6GBqYGBqamJkaOxsSoAQDD-Cgp</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Multi-processor architecture and method</title><source>esp@cenet</source><creator>MOREIN STEPHEN ; SOLKI SHAHIN ; GROSSMAN MARK S</creator><creatorcontrib>MOREIN STEPHEN ; SOLKI SHAHIN ; GROSSMAN MARK S</creatorcontrib><description>Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC Embodiments is usable with known bus protocols.</description><language>eng</language><subject>ADVERTISING ; ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION ; CALCULATING ; COMPUTING ; COUNTING ; CRYPTOGRAPHY ; DISPLAY ; EDUCATION ; ELECTRIC DIGITAL DATA PROCESSING ; IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ; PHYSICS ; SEALS</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20151028&DB=EPODOC&CC=CN&NR=105005542A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20151028&DB=EPODOC&CC=CN&NR=105005542A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MOREIN STEPHEN</creatorcontrib><creatorcontrib>SOLKI SHAHIN</creatorcontrib><creatorcontrib>GROSSMAN MARK S</creatorcontrib><title>Multi-processor architecture and method</title><description>Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC Embodiments is usable with known bus protocols.</description><subject>ADVERTISING</subject><subject>ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>CRYPTOGRAPHY</subject><subject>DISPLAY</subject><subject>EDUCATION</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>IMAGE DATA PROCESSING OR GENERATION, IN GENERAL</subject><subject>PHYSICS</subject><subject>SEALS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFD3Lc0pydQtKMpPTi0uzi9SSCxKzsgsSU0uKS1KVUjMS1HITS3JyE_hYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxzn6GBqYGBqamJkaOxsSoAQDD-Cgp</recordid><startdate>20151028</startdate><enddate>20151028</enddate><creator>MOREIN STEPHEN</creator><creator>SOLKI SHAHIN</creator><creator>GROSSMAN MARK S</creator><scope>EVB</scope></search><sort><creationdate>20151028</creationdate><title>Multi-processor architecture and method</title><author>MOREIN STEPHEN ; SOLKI SHAHIN ; GROSSMAN MARK S</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN105005542A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2015</creationdate><topic>ADVERTISING</topic><topic>ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>CRYPTOGRAPHY</topic><topic>DISPLAY</topic><topic>EDUCATION</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>IMAGE DATA PROCESSING OR GENERATION, IN GENERAL</topic><topic>PHYSICS</topic><topic>SEALS</topic><toplevel>online_resources</toplevel><creatorcontrib>MOREIN STEPHEN</creatorcontrib><creatorcontrib>SOLKI SHAHIN</creatorcontrib><creatorcontrib>GROSSMAN MARK S</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MOREIN STEPHEN</au><au>SOLKI SHAHIN</au><au>GROSSMAN MARK S</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Multi-processor architecture and method</title><date>2015-10-28</date><risdate>2015</risdate><abstract>Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC Embodiments is usable with known bus protocols.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | ADVERTISING ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION CALCULATING COMPUTING COUNTING CRYPTOGRAPHY DISPLAY EDUCATION ELECTRIC DIGITAL DATA PROCESSING IMAGE DATA PROCESSING OR GENERATION, IN GENERAL PHYSICS SEALS |
| title | Multi-processor architecture and method |
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