SEMICONDUCTOR DEVICE
The present invention provides a semiconductor device with an improved withstand voltage performance. The semiconductor device includes a substrate, a first conducting layer, a diffusion layer, a first insulating layer, a second conducting layer, a second insulating layer and a third insulating laye...
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| creator | HIDEKI SEKIGUCHI |
| description | The present invention provides a semiconductor device with an improved withstand voltage performance. The semiconductor device includes a substrate, a first conducting layer, a diffusion layer, a first insulating layer, a second conducting layer, a second insulating layer and a third insulating layer. The substrate has a primary face including an inner region containing semiconductor elements and a peripheral region around the inner region. The first conducting layer is arranged on the periphery region and includes a first peripheral conducting portion and a first inner conducting portion. The diffusion layer is arranged on the peripheral region and includes a peripheral diffusion layer and an inner diffusion layer between the inner region and the first peripheral conducting portion when the primary face is projected. The first insulating layer is arranged between the first peripheral conducting portion and the peripheral region, and includes a peripheral insulating portion and an inner insulating portion when the primary face is projected. The second conducting layer is arranged between the peripheral region and the first peripheral conducting portion, and includes a second peripheral conducting portion between the inner insulating portion and the first peripheral conducting portion, a second inner conducting portion between the peripheral diffusion portion and the first inner conducting layer, and a middle conducting layer. |
| format | Patent |
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The semiconductor device includes a substrate, a first conducting layer, a diffusion layer, a first insulating layer, a second conducting layer, a second insulating layer and a third insulating layer. The substrate has a primary face including an inner region containing semiconductor elements and a peripheral region around the inner region. The first conducting layer is arranged on the periphery region and includes a first peripheral conducting portion and a first inner conducting portion. The diffusion layer is arranged on the peripheral region and includes a peripheral diffusion layer and an inner diffusion layer between the inner region and the first peripheral conducting portion when the primary face is projected. The first insulating layer is arranged between the first peripheral conducting portion and the peripheral region, and includes a peripheral insulating portion and an inner insulating portion when the primary face is projected. The second conducting layer is arranged between the peripheral region and the first peripheral conducting portion, and includes a second peripheral conducting portion between the inner insulating portion and the first peripheral conducting portion, a second inner conducting portion between the peripheral diffusion portion and the first inner conducting layer, and a middle conducting layer.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150916&DB=EPODOC&CC=CN&NR=104916671A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150916&DB=EPODOC&CC=CN&NR=104916671A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HIDEKI SEKIGUCHI</creatorcontrib><title>SEMICONDUCTOR DEVICE</title><description>The present invention provides a semiconductor device with an improved withstand voltage performance. The semiconductor device includes a substrate, a first conducting layer, a diffusion layer, a first insulating layer, a second conducting layer, a second insulating layer and a third insulating layer. The substrate has a primary face including an inner region containing semiconductor elements and a peripheral region around the inner region. The first conducting layer is arranged on the periphery region and includes a first peripheral conducting portion and a first inner conducting portion. The diffusion layer is arranged on the peripheral region and includes a peripheral diffusion layer and an inner diffusion layer between the inner region and the first peripheral conducting portion when the primary face is projected. The first insulating layer is arranged between the first peripheral conducting portion and the peripheral region, and includes a peripheral insulating portion and an inner insulating portion when the primary face is projected. The second conducting layer is arranged between the peripheral region and the first peripheral conducting portion, and includes a second peripheral conducting portion between the inner insulating portion and the first peripheral conducting portion, a second inner conducting portion between the peripheral diffusion portion and the first inner conducting layer, and a middle conducting layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAJdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfHOfoYGJpaGZmbmho7GxKgBAIFuHrA</recordid><startdate>20150916</startdate><enddate>20150916</enddate><creator>HIDEKI SEKIGUCHI</creator><scope>EVB</scope></search><sort><creationdate>20150916</creationdate><title>SEMICONDUCTOR DEVICE</title><author>HIDEKI SEKIGUCHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN104916671A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2015</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>HIDEKI SEKIGUCHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HIDEKI SEKIGUCHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE</title><date>2015-09-16</date><risdate>2015</risdate><abstract>The present invention provides a semiconductor device with an improved withstand voltage performance. The semiconductor device includes a substrate, a first conducting layer, a diffusion layer, a first insulating layer, a second conducting layer, a second insulating layer and a third insulating layer. The substrate has a primary face including an inner region containing semiconductor elements and a peripheral region around the inner region. The first conducting layer is arranged on the periphery region and includes a first peripheral conducting portion and a first inner conducting portion. The diffusion layer is arranged on the peripheral region and includes a peripheral diffusion layer and an inner diffusion layer between the inner region and the first peripheral conducting portion when the primary face is projected. The first insulating layer is arranged between the first peripheral conducting portion and the peripheral region, and includes a peripheral insulating portion and an inner insulating portion when the primary face is projected. The second conducting layer is arranged between the peripheral region and the first peripheral conducting portion, and includes a second peripheral conducting portion between the inner insulating portion and the first peripheral conducting portion, a second inner conducting portion between the peripheral diffusion portion and the first inner conducting layer, and a middle conducting layer.</abstract><oa>free_for_read</oa></addata></record> |
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| language | eng |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | SEMICONDUCTOR DEVICE |
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