Read control circuit for retention memory

A read control circuit for a retention memory comprises a power converter outputting direct current, a retention memory unit, a read/write circuit, a voltage regulator and a CPU (control processing unit), wherein the output end of the power converter is connected with the read/write circuit; the voltage regulator provides a voltage-adjustable third direct-current power supply, the voltage of the third direct-current power supply ranges from a preset minimum value to a preset maximum value, and the preset maximum voltage value is equal to a voltage value of the power converter; the control processing unit controls the voltage of the third direct-current power supply to increase from the preset minimum value to the preset maximum value when the CPU is switched to a work state from a standby state and controls the voltage of the third direct-current power supply to decrease from the preset maximum value to the preset minimum value when the CPU is switched to the standby state from the work state, the output end of the CPU is connected with the control end of the voltage regulator, and the output end of the voltage regulator is connected with a power supply end of the retention memory unit. The power voltage of the retention memory can be reduced to a lower value when the CPU is ready to start the standby state due to the voltage regulator, and accordingly, the consumption of static current of the retention memory is reduced.