Nonvolatile semiconductor storage device
According to the present invention, a memory array (10) is provided with: a resistance change-type memory cell array (11) that is configured by connecting a first cell transistor and a resistance change element in series; and a reference cell array (12) that is configured by connecting a second cell...
Gespeichert in:
Hauptverfasser: | , , , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | KOUNO KAZUYUKI TAKAHASHI KEITA MURAKUKI YASUO ISHITOBI YURIKO NAKAYAMA MASAYOSHI UEDA TAKANORI |
description | According to the present invention, a memory array (10) is provided with: a resistance change-type memory cell array (11) that is configured by connecting a first cell transistor and a resistance change element in series; and a reference cell array (12) that is configured by connecting a second cell transistor and a resistance element in series; the second cell transistor of the reference cell array (12) being connected to a reference source line (RSL) and the resistance element being connected to a reference bit line (RBL), a dummy memory cell inside the memory cell array (11) being connected to the reference bit line (RBL), and both ends of the resistance change element of the dummy memory cell being short-circuited by the reference bit line (RBL). |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN104685572A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN104685572A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN104685572A3</originalsourceid><addsrcrecordid>eNrjZNDwy88ry89JLMnMSVUoTs3NTM7PSylNLskvUigGEonpqQopqWWZyak8DKxpiTnFqbxQmptB0c01xNlDN7UgPz61uCAxOTUvtSTe2c_QwMTMwtTU3MjRmBg1ABQfKOo</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Nonvolatile semiconductor storage device</title><source>esp@cenet</source><creator>KOUNO KAZUYUKI ; TAKAHASHI KEITA ; MURAKUKI YASUO ; ISHITOBI YURIKO ; NAKAYAMA MASAYOSHI ; UEDA TAKANORI</creator><creatorcontrib>KOUNO KAZUYUKI ; TAKAHASHI KEITA ; MURAKUKI YASUO ; ISHITOBI YURIKO ; NAKAYAMA MASAYOSHI ; UEDA TAKANORI</creatorcontrib><description>According to the present invention, a memory array (10) is provided with: a resistance change-type memory cell array (11) that is configured by connecting a first cell transistor and a resistance change element in series; and a reference cell array (12) that is configured by connecting a second cell transistor and a resistance element in series; the second cell transistor of the reference cell array (12) being connected to a reference source line (RSL) and the resistance element being connected to a reference bit line (RBL), a dummy memory cell inside the memory cell array (11) being connected to the reference bit line (RBL), and both ends of the resistance change element of the dummy memory cell being short-circuited by the reference bit line (RBL).</description><language>eng</language><subject>ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150603&DB=EPODOC&CC=CN&NR=104685572A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150603&DB=EPODOC&CC=CN&NR=104685572A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KOUNO KAZUYUKI</creatorcontrib><creatorcontrib>TAKAHASHI KEITA</creatorcontrib><creatorcontrib>MURAKUKI YASUO</creatorcontrib><creatorcontrib>ISHITOBI YURIKO</creatorcontrib><creatorcontrib>NAKAYAMA MASAYOSHI</creatorcontrib><creatorcontrib>UEDA TAKANORI</creatorcontrib><title>Nonvolatile semiconductor storage device</title><description>According to the present invention, a memory array (10) is provided with: a resistance change-type memory cell array (11) that is configured by connecting a first cell transistor and a resistance change element in series; and a reference cell array (12) that is configured by connecting a second cell transistor and a resistance element in series; the second cell transistor of the reference cell array (12) being connected to a reference source line (RSL) and the resistance element being connected to a reference bit line (RBL), a dummy memory cell inside the memory cell array (11) being connected to the reference bit line (RBL), and both ends of the resistance change element of the dummy memory cell being short-circuited by the reference bit line (RBL).</description><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNDwy88ry89JLMnMSVUoTs3NTM7PSylNLskvUigGEonpqQopqWWZyak8DKxpiTnFqbxQmptB0c01xNlDN7UgPz61uCAxOTUvtSTe2c_QwMTMwtTU3MjRmBg1ABQfKOo</recordid><startdate>20150603</startdate><enddate>20150603</enddate><creator>KOUNO KAZUYUKI</creator><creator>TAKAHASHI KEITA</creator><creator>MURAKUKI YASUO</creator><creator>ISHITOBI YURIKO</creator><creator>NAKAYAMA MASAYOSHI</creator><creator>UEDA TAKANORI</creator><scope>EVB</scope></search><sort><creationdate>20150603</creationdate><title>Nonvolatile semiconductor storage device</title><author>KOUNO KAZUYUKI ; TAKAHASHI KEITA ; MURAKUKI YASUO ; ISHITOBI YURIKO ; NAKAYAMA MASAYOSHI ; UEDA TAKANORI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN104685572A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2015</creationdate><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>KOUNO KAZUYUKI</creatorcontrib><creatorcontrib>TAKAHASHI KEITA</creatorcontrib><creatorcontrib>MURAKUKI YASUO</creatorcontrib><creatorcontrib>ISHITOBI YURIKO</creatorcontrib><creatorcontrib>NAKAYAMA MASAYOSHI</creatorcontrib><creatorcontrib>UEDA TAKANORI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KOUNO KAZUYUKI</au><au>TAKAHASHI KEITA</au><au>MURAKUKI YASUO</au><au>ISHITOBI YURIKO</au><au>NAKAYAMA MASAYOSHI</au><au>UEDA TAKANORI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Nonvolatile semiconductor storage device</title><date>2015-06-03</date><risdate>2015</risdate><abstract>According to the present invention, a memory array (10) is provided with: a resistance change-type memory cell array (11) that is configured by connecting a first cell transistor and a resistance change element in series; and a reference cell array (12) that is configured by connecting a second cell transistor and a resistance element in series; the second cell transistor of the reference cell array (12) being connected to a reference source line (RSL) and the resistance element being connected to a reference bit line (RBL), a dummy memory cell inside the memory cell array (11) being connected to the reference bit line (RBL), and both ends of the resistance change element of the dummy memory cell being short-circuited by the reference bit line (RBL).</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_CN104685572A |
source | esp@cenet |
subjects | ELECTRICITY INFORMATION STORAGE PHYSICS STATIC STORES |
title | Nonvolatile semiconductor storage device |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T10%3A41%3A31IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KOUNO%20KAZUYUKI&rft.date=2015-06-03&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN104685572A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |