Low-load mirror image summator

The invention discloses a low-load mirror image summator which comprises a carry input port C[1], n addend binary input ports A[1]...A[n], n augend binary input ports B[1]...B[n], n+1 binary input ports S[1]... S[n+1], a first independent phase inverter, a second independent phase inverter, n PGTX g...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser:	CHEN XIN, XIA HUAN, ZHANG BO, HU WEI, HUANG HUI, CHEN QIANG, DUAN QIANNI, ZHANG WANQIAO, ZHOU JIANGYAN, CHEN RONGTAO
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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Beschreibung
Zusammenfassung:	The invention discloses a low-load mirror image summator which comprises a carry input port C[1], n addend binary input ports A[1]...A[n], n augend binary input ports B[1]...B[n], n+1 binary input ports S[1]... S[n+1], a first independent phase inverter, a second independent phase inverter, n PGTX generating circuits, an n-level carry generation circuit and n summing circuits, wherein n is an integer larger than or equal to 2. According to the low-load mirror image summator, low-order carry is generated while high-order carry is generated, the load of add operation is small, operation is fast, the number of MOS tubes required is small during layout design, and layout design is easy.